gpu: nvgpu: define runlist level in common code

All the runlist levels NVGPU_RUNLIST_INTERLEAVE_LEVEL_* are declared in linux
specific uapi header and used in common code
But since common code should be linux-independent, move these uses out of
common code

Define new runlist levels NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_* in common code
and use them wherever required

Add new API nvgpu_get_common_runlist_level() to get common runlist level of
the form NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_* from linux specific runlist
level of the form NVGPU_RUNLIST_INTERLEAVE_LEVEL_*

Jira NVGPU-259

Change-Id: Ic19239f0f8275683d5d1b981df530acd90e6dfbb
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1594327
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 4 insertions, 4 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c
index 6c607ae2..229e3782 100644
--- a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c
@@ -322,9 +322,9 @@ int gk20a_channel_set_runlist_interleave(struct channel_gk20a *ch,
         }
 
         switch (level) {
-        case NVGPU_RUNLIST_INTERLEAVE_LEVEL_LOW:
-        case NVGPU_RUNLIST_INTERLEAVE_LEVEL_MEDIUM:
-        case NVGPU_RUNLIST_INTERLEAVE_LEVEL_HIGH:
+        case NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_LOW:
+        case NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_MEDIUM:
+        case NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_HIGH:
                 ret = g->ops.fifo.set_runlist_interleave(g, ch->chid,
                                                         false, 0, level);
                 break;
@@ -858,7 +858,7 @@ struct channel_gk20a *gk20a_open_new_channel(struct gk20a *g,
         ch->has_timedout = false;
         ch->wdt_enabled = true;
         ch->obj_class = 0;
-        ch->interleave_level = NVGPU_RUNLIST_INTERLEAVE_LEVEL_LOW;
+        ch->interleave_level = NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_LOW;
         ch->timeslice_us = g->timeslice_low_priority_us;
 #ifdef CONFIG_TEGRA_19x_GPU
         memset(&ch->t19x, 0, sizeof(struct channel_t19x));