diff options
author | Richard Zhao <rizhao@nvidia.com> | 2016-08-12 20:10:28 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2016-08-18 18:03:54 -0400 |
commit | 198b895a881ca067a2411b7367579cb1d594ab5a (patch) | |
tree | 90e667382a589de9ba4d97bf511ca6bd42efe03c /drivers/gpu/nvgpu/gk20a/channel_gk20a.c | |
parent | deffbf8ee2017d4ea804f35946673dd0f6e0fcf2 (diff) |
gpu: nvgpu: use force_reset_ch in ch wdt handler
- let force_reset_ch pass down err code
- force_reset_ch callback can cover vgpu too.
Bug 1776876
JIRA VFND-2151
Change-Id: I48f7890294c6455247198e0cab5f21f83f61f0e1
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/1202255
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/channel_gk20a.c')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/channel_gk20a.c | 52 |
1 files changed, 5 insertions, 47 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c index a8a39302..41fced99 100644 --- a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c | |||
@@ -1721,10 +1721,6 @@ static void gk20a_channel_timeout_handler(struct work_struct *work) | |||
1721 | struct channel_gk20a_job *job; | 1721 | struct channel_gk20a_job *job; |
1722 | struct gk20a *g; | 1722 | struct gk20a *g; |
1723 | struct channel_gk20a *ch; | 1723 | struct channel_gk20a *ch; |
1724 | struct channel_gk20a *failing_ch; | ||
1725 | u32 engine_id; | ||
1726 | int id = -1; | ||
1727 | bool is_tsg = false; | ||
1728 | 1724 | ||
1729 | ch = container_of(to_delayed_work(work), struct channel_gk20a, | 1725 | ch = container_of(to_delayed_work(work), struct channel_gk20a, |
1730 | timeout.wq); | 1726 | timeout.wq); |
@@ -1746,16 +1742,11 @@ static void gk20a_channel_timeout_handler(struct work_struct *work) | |||
1746 | ch->timeout.initialized = false; | 1742 | ch->timeout.initialized = false; |
1747 | mutex_unlock(&ch->timeout.lock); | 1743 | mutex_unlock(&ch->timeout.lock); |
1748 | 1744 | ||
1749 | if (gr_gk20a_disable_ctxsw(g)) { | ||
1750 | gk20a_err(dev_from_gk20a(g), "Unable to disable ctxsw!"); | ||
1751 | goto fail_unlock; | ||
1752 | } | ||
1753 | |||
1754 | if (gk20a_fence_is_expired(job->post_fence)) { | 1745 | if (gk20a_fence_is_expired(job->post_fence)) { |
1755 | gk20a_err(dev_from_gk20a(g), | 1746 | gk20a_err(dev_from_gk20a(g), |
1756 | "Timed out fence is expired on c=%d!", | 1747 | "Timed out fence is expired on c=%d!", |
1757 | ch->hw_chid); | 1748 | ch->hw_chid); |
1758 | goto fail_enable_ctxsw; | 1749 | goto fail_unlock; |
1759 | } | 1750 | } |
1760 | 1751 | ||
1761 | gk20a_err(dev_from_gk20a(g), "Confirmed: job on channel %d timed out", | 1752 | gk20a_err(dev_from_gk20a(g), "Confirmed: job on channel %d timed out", |
@@ -1764,43 +1755,9 @@ static void gk20a_channel_timeout_handler(struct work_struct *work) | |||
1764 | gk20a_debug_dump(g->dev); | 1755 | gk20a_debug_dump(g->dev); |
1765 | gk20a_gr_debug_dump(g->dev); | 1756 | gk20a_gr_debug_dump(g->dev); |
1766 | 1757 | ||
1767 | /* Get failing engine data */ | 1758 | g->ops.fifo.force_reset_ch(ch, |
1768 | engine_id = gk20a_fifo_get_failing_engine_data(g, &id, &is_tsg); | 1759 | NVGPU_CHANNEL_FIFO_ERROR_IDLE_TIMEOUT, true); |
1769 | |||
1770 | if (!gk20a_fifo_is_valid_engine_id(g, engine_id)) { | ||
1771 | /* If no failing engine, abort the channels */ | ||
1772 | if (gk20a_is_channel_marked_as_tsg(ch)) { | ||
1773 | struct tsg_gk20a *tsg = &g->fifo.tsg[ch->tsgid]; | ||
1774 | |||
1775 | gk20a_fifo_set_ctx_mmu_error_tsg(g, tsg); | ||
1776 | gk20a_fifo_abort_tsg(g, ch->tsgid, false); | ||
1777 | } else { | ||
1778 | gk20a_fifo_set_ctx_mmu_error_ch(g, ch); | ||
1779 | gk20a_channel_abort(ch, false); | ||
1780 | } | ||
1781 | } else { | ||
1782 | /* If failing engine, trigger recovery */ | ||
1783 | failing_ch = gk20a_channel_get(&g->fifo.channel[id]); | ||
1784 | if (!failing_ch) | ||
1785 | goto fail_enable_ctxsw; | ||
1786 | |||
1787 | if (failing_ch->hw_chid != ch->hw_chid) { | ||
1788 | gk20a_channel_timeout_start(ch, job); | ||
1789 | |||
1790 | mutex_lock(&failing_ch->timeout.lock); | ||
1791 | failing_ch->timeout.initialized = false; | ||
1792 | mutex_unlock(&failing_ch->timeout.lock); | ||
1793 | } | ||
1794 | |||
1795 | gk20a_fifo_recover(g, BIT(engine_id), | ||
1796 | failing_ch->hw_chid, is_tsg, | ||
1797 | true, failing_ch->timeout_debug_dump); | ||
1798 | |||
1799 | gk20a_channel_put(failing_ch); | ||
1800 | } | ||
1801 | 1760 | ||
1802 | fail_enable_ctxsw: | ||
1803 | gr_gk20a_enable_ctxsw(g); | ||
1804 | fail_unlock: | 1761 | fail_unlock: |
1805 | mutex_unlock(&g->ch_wdt_lock); | 1762 | mutex_unlock(&g->ch_wdt_lock); |
1806 | gk20a_channel_put(ch); | 1763 | gk20a_channel_put(ch); |
@@ -3231,7 +3188,8 @@ long gk20a_channel_ioctl(struct file *filp, | |||
3231 | __func__, cmd); | 3188 | __func__, cmd); |
3232 | break; | 3189 | break; |
3233 | } | 3190 | } |
3234 | err = ch->g->ops.fifo.force_reset_ch(ch, true); | 3191 | err = ch->g->ops.fifo.force_reset_ch(ch, |
3192 | NVGPU_CHANNEL_RESETCHANNEL_VERIF_ERROR, true); | ||
3235 | gk20a_idle(dev); | 3193 | gk20a_idle(dev); |
3236 | break; | 3194 | break; |
3237 | case NVGPU_IOCTL_CHANNEL_EVENT_ID_CTRL: | 3195 | case NVGPU_IOCTL_CHANNEL_EVENT_ID_CTRL: |