gpu: nvgpu: Move programming of host registers to fifo

Move code that touches host registers and instance block to fifo HAL.
This involves adding HAL ops for the fifo HAL functions that get
called from outside fifo. This clears responsibility of channel by
leaving it only managing channels in software and push buffers.

channel had member ramfc defined, but it was not used, to remove it.

pbdma_acquire_val consisted both of channel logic and hardware
programming. The channel logic was moved to the caller and only
hardware programming was moved.

Change-Id: Id005787f6cc91276b767e8e86325caf966913de9
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1322423
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 2 insertions, 2 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c
index 5dfd2309..418572a1 100644
--- a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c
@@ -488,7 +488,7 @@ u32 gk20a_ce_create_context_with_cb(struct device *dev,
 
         /* -1 means default channel priority */
         if (priority != -1) {
-                err = gk20a_channel_set_priority(ce_ctx->ch, priority);
+                err = gk20a_fifo_set_priority(ce_ctx->ch, priority);
                 if (err) {
                         gk20a_err(ce_ctx->dev,
                                 "ce: could not set the channel priority for CE context");
@@ -498,7 +498,7 @@ u32 gk20a_ce_create_context_with_cb(struct device *dev,
 
         /* -1 means default channel timeslice value */
         if (timeslice != -1) {
-                err = gk20a_channel_set_timeslice(ce_ctx->ch, timeslice);
+                err = gk20a_fifo_set_timeslice(ce_ctx->ch, timeslice);
                 if (err) {
                         gk20a_err(ce_ctx->dev,
                                 "ce: could not set the channel timeslice value for CE context");