diff options
author | Terje Bergstrom <tbergstrom@nvidia.com> | 2018-04-18 22:39:46 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-05-09 21:26:04 -0400 |
commit | dd739fcb039d51606e9a5454ec0aab17bcb01965 (patch) | |
tree | 806ba8575d146367ad1be00086ca0cdae35a6b28 /drivers/gpu/nvgpu/gk20a/ce2_gk20a.c | |
parent | 7e66f2a63d4855e763fa768047dfc32f6f96b771 (diff) |
gpu: nvgpu: Remove gk20a_dbg* functions
Switch all logging to nvgpu_log*(). gk20a_dbg* macros are
intentionally left there because of use from other repositories.
Because the new functions do not work without a pointer to struct
gk20a, and piping it just for logging is excessive, some log messages
are deleted.
Change-Id: I00e22e75fe4596a330bb0282ab4774b3639ee31e
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1704148
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/ce2_gk20a.c')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/ce2_gk20a.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c index 0280bbbb..086d4e7b 100644 --- a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c | |||
@@ -50,21 +50,21 @@ | |||
50 | 50 | ||
51 | static u32 ce2_nonblockpipe_isr(struct gk20a *g, u32 fifo_intr) | 51 | static u32 ce2_nonblockpipe_isr(struct gk20a *g, u32 fifo_intr) |
52 | { | 52 | { |
53 | gk20a_dbg(gpu_dbg_intr, "ce2 non-blocking pipe interrupt\n"); | 53 | nvgpu_log(g, gpu_dbg_intr, "ce2 non-blocking pipe interrupt\n"); |
54 | 54 | ||
55 | return ce2_intr_status_nonblockpipe_pending_f(); | 55 | return ce2_intr_status_nonblockpipe_pending_f(); |
56 | } | 56 | } |
57 | 57 | ||
58 | static u32 ce2_blockpipe_isr(struct gk20a *g, u32 fifo_intr) | 58 | static u32 ce2_blockpipe_isr(struct gk20a *g, u32 fifo_intr) |
59 | { | 59 | { |
60 | gk20a_dbg(gpu_dbg_intr, "ce2 blocking pipe interrupt\n"); | 60 | nvgpu_log(g, gpu_dbg_intr, "ce2 blocking pipe interrupt\n"); |
61 | 61 | ||
62 | return ce2_intr_status_blockpipe_pending_f(); | 62 | return ce2_intr_status_blockpipe_pending_f(); |
63 | } | 63 | } |
64 | 64 | ||
65 | static u32 ce2_launcherr_isr(struct gk20a *g, u32 fifo_intr) | 65 | static u32 ce2_launcherr_isr(struct gk20a *g, u32 fifo_intr) |
66 | { | 66 | { |
67 | gk20a_dbg(gpu_dbg_intr, "ce2 launch error interrupt\n"); | 67 | nvgpu_log(g, gpu_dbg_intr, "ce2 launch error interrupt\n"); |
68 | 68 | ||
69 | return ce2_intr_status_launcherr_pending_f(); | 69 | return ce2_intr_status_launcherr_pending_f(); |
70 | } | 70 | } |
@@ -74,7 +74,7 @@ void gk20a_ce2_isr(struct gk20a *g, u32 inst_id, u32 pri_base) | |||
74 | u32 ce2_intr = gk20a_readl(g, ce2_intr_status_r()); | 74 | u32 ce2_intr = gk20a_readl(g, ce2_intr_status_r()); |
75 | u32 clear_intr = 0; | 75 | u32 clear_intr = 0; |
76 | 76 | ||
77 | gk20a_dbg(gpu_dbg_intr, "ce2 isr %08x\n", ce2_intr); | 77 | nvgpu_log(g, gpu_dbg_intr, "ce2 isr %08x\n", ce2_intr); |
78 | 78 | ||
79 | /* clear blocking interrupts: they exibit broken behavior */ | 79 | /* clear blocking interrupts: they exibit broken behavior */ |
80 | if (ce2_intr & ce2_intr_status_blockpipe_pending_f()) | 80 | if (ce2_intr & ce2_intr_status_blockpipe_pending_f()) |
@@ -92,7 +92,7 @@ int gk20a_ce2_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base) | |||
92 | int ops = 0; | 92 | int ops = 0; |
93 | u32 ce2_intr = gk20a_readl(g, ce2_intr_status_r()); | 93 | u32 ce2_intr = gk20a_readl(g, ce2_intr_status_r()); |
94 | 94 | ||
95 | gk20a_dbg(gpu_dbg_intr, "ce2 nonstall isr %08x\n", ce2_intr); | 95 | nvgpu_log(g, gpu_dbg_intr, "ce2 nonstall isr %08x\n", ce2_intr); |
96 | 96 | ||
97 | if (ce2_intr & ce2_intr_status_nonblockpipe_pending_f()) { | 97 | if (ce2_intr & ce2_intr_status_nonblockpipe_pending_f()) { |
98 | gk20a_writel(g, ce2_intr_status_r(), | 98 | gk20a_writel(g, ce2_intr_status_r(), |
@@ -340,7 +340,7 @@ int gk20a_init_ce_support(struct gk20a *g) | |||
340 | return 0; | 340 | return 0; |
341 | } | 341 | } |
342 | 342 | ||
343 | gk20a_dbg(gpu_dbg_fn, "ce: init"); | 343 | nvgpu_log(g, gpu_dbg_fn, "ce: init"); |
344 | 344 | ||
345 | err = nvgpu_mutex_init(&ce_app->app_mutex); | 345 | err = nvgpu_mutex_init(&ce_app->app_mutex); |
346 | if (err) | 346 | if (err) |
@@ -355,7 +355,7 @@ int gk20a_init_ce_support(struct gk20a *g) | |||
355 | ce_app->app_state = NVGPU_CE_ACTIVE; | 355 | ce_app->app_state = NVGPU_CE_ACTIVE; |
356 | 356 | ||
357 | nvgpu_mutex_release(&ce_app->app_mutex); | 357 | nvgpu_mutex_release(&ce_app->app_mutex); |
358 | gk20a_dbg(gpu_dbg_cde_ctx, "ce: init finished"); | 358 | nvgpu_log(g, gpu_dbg_cde_ctx, "ce: init finished"); |
359 | 359 | ||
360 | return 0; | 360 | return 0; |
361 | } | 361 | } |