gpu: nvgpu: hal for timestamps correlation

In order to perform timestamps correlation for FECS
traces, we need to collect GPU / GPU timestamps
samples. In virtualization case, it is possible for
a guest to get GPU timestamps by using read_ptimer.
However, if the CPU timestamp is read on guest side,
and the GPU timestamp is read on vm-server side,
then it introduces some latency that will create an
artificial offset for GPU timestamps (~2 us in
average). For better CPU / GPU timestamps correlation,
Added a command to collect all timestamps on vm-server
side.

Bug 1900475

Change-Id: Idfdc6ae4c16c501dc5e00053a5b75932c55148d6
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/1472447
(cherry picked from commit 56f56b5cd9d2e75cf7d2613b5e115bfebdbee0ce)
Reviewed-on: http://git-master/r/1489183
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 61 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/bus_gk20a.c b/drivers/gpu/nvgpu/gk20a/bus_gk20a.c
index 52ef08e4..7f0ca013 100644
--- a/drivers/gpu/nvgpu/gk20a/bus_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/bus_gk20a.c
@@ -128,6 +128,66 @@ int gk20a_read_ptimer(struct gk20a *g, u64 *value)
         return -EBUSY;
 }
 
+static inline u64 get_cpu_timestamp_tsc(void)
+{
+        return ((u64) get_cycles());
+}
+
+static inline u64 get_cpu_timestamp_jiffies(void)
+{
+        return (get_jiffies_64() - INITIAL_JIFFIES);
+}
+
+static inline u64 get_cpu_timestamp_timeofday(void)
+{
+        struct timeval tv;
+
+        do_gettimeofday(&tv);
+        return timeval_to_jiffies(&tv);
+}
+
+int gk20a_get_timestamps_zipper(struct gk20a *g,
+                u32 source_id, u32 count,
+                struct nvgpu_cpu_time_correlation_sample *samples)
+{
+        int err = 0;
+        unsigned int i = 0;
+        u64 (*get_cpu_timestamp)(void) = NULL;
+
+        switch (source_id) {
+        case NVGPU_GPU_GET_CPU_TIME_CORRELATION_INFO_SRC_ID_TSC:
+                get_cpu_timestamp = get_cpu_timestamp_tsc;
+                break;
+        case NVGPU_GPU_GET_CPU_TIME_CORRELATION_INFO_SRC_ID_JIFFIES:
+                get_cpu_timestamp = get_cpu_timestamp_jiffies;
+                break;
+        case NVGPU_GPU_GET_CPU_TIME_CORRELATION_INFO_SRC_ID_TIMEOFDAY:
+                get_cpu_timestamp = get_cpu_timestamp_timeofday;
+                break;
+        default:
+                nvgpu_err(g, "invalid cpu clock source id\n");
+                return -EINVAL;
+        }
+
+        if (gk20a_busy(g)) {
+                nvgpu_err(g, "GPU not powered on\n");
+                err = -EINVAL;
+                goto end;
+        }
+
+        for (i = 0; i < count; i++) {
+                err = g->ops.bus.read_ptimer(g, &samples[i].gpu_timestamp);
+                if (err)
+                        return err;
+
+                samples[i].cpu_timestamp = get_cpu_timestamp();
+        }
+
+end:
+        gk20a_idle(g);
+        return err;
+}
+
 static int gk20a_bus_bar1_bind(struct gk20a *g, struct nvgpu_mem *bar1_inst)
 {
         u64 iova = gk20a_mm_inst_block_addr(g, bar1_inst);
@@ -150,5 +210,6 @@ void gk20a_init_bus(struct gpu_ops *gops)
         gops->bus.init_hw = gk20a_bus_init_hw;
         gops->bus.isr = gk20a_bus_isr;
         gops->bus.read_ptimer = gk20a_read_ptimer;
+        gops->bus.get_timestamps_zipper = gk20a_get_timestamps_zipper;
         gops->bus.bar1_bind = gk20a_bus_bar1_bind;
 }