summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/nvgpu/gk20a/bus_gk20a.c
diff options
context:
space:
mode:
authorTerje Bergstrom <tbergstrom@nvidia.com>2018-04-06 17:16:10 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-05-25 13:15:40 -0400
commit2dbf961365822e38ac6b7266388fcfa503f6e52f (patch)
treed3ee4e3698b80c2d9a4174547c42e66098b63750 /drivers/gpu/nvgpu/gk20a/bus_gk20a.c
parent775c69af8cffbd3c11cda027a99ad9d588e09f95 (diff)
gpu: nvgpu: Move bus HAL to common
Move implementation of bus HAL to common/bus. Change-Id: Ia89350f9d94f3ccfd5500a340e6a677cd7d4cfaa Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1726337 GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/bus_gk20a.c')
-rw-r--r--drivers/gpu/nvgpu/gk20a/bus_gk20a.c188
1 files changed, 0 insertions, 188 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/bus_gk20a.c b/drivers/gpu/nvgpu/gk20a/bus_gk20a.c
deleted file mode 100644
index ab75e8d7..00000000
--- a/drivers/gpu/nvgpu/gk20a/bus_gk20a.c
+++ /dev/null
@@ -1,188 +0,0 @@
1/*
2 * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#include <nvgpu/page_allocator.h>
24#include <nvgpu/enabled.h>
25#include <nvgpu/log.h>
26#include <nvgpu/soc.h>
27#include <nvgpu/bus.h>
28#include <nvgpu/mm.h>
29
30#include "gk20a.h"
31#include "bus_gk20a.h"
32
33#include <nvgpu/hw/gk20a/hw_bus_gk20a.h>
34#include <nvgpu/hw/gk20a/hw_mc_gk20a.h>
35#include <nvgpu/hw/gk20a/hw_gr_gk20a.h>
36#include <nvgpu/hw/gk20a/hw_timer_gk20a.h>
37#include <nvgpu/hw/gk20a/hw_pri_ringstation_sys_gk20a.h>
38#include <nvgpu/hw/gk20a/hw_pri_ringstation_gpc_gk20a.h>
39#include <nvgpu/hw/gk20a/hw_pri_ringstation_fbp_gk20a.h>
40
41void gk20a_bus_init_hw(struct gk20a *g)
42{
43 u32 timeout_period, intr_en_mask = 0;
44
45 if (nvgpu_platform_is_silicon(g))
46 timeout_period = g->default_pri_timeout ?
47 g->default_pri_timeout : 0x186A0;
48 else
49 timeout_period = 0x186A0;
50
51 if (nvgpu_platform_is_silicon(g) || nvgpu_platform_is_fpga(g)) {
52 intr_en_mask = bus_intr_en_0_pri_squash_m() |
53 bus_intr_en_0_pri_fecserr_m() |
54 bus_intr_en_0_pri_timeout_m();
55 gk20a_writel(g,
56 timer_pri_timeout_r(),
57 timer_pri_timeout_period_f(timeout_period) |
58 timer_pri_timeout_en_en_enabled_f());
59
60 } else {
61 gk20a_writel(g,
62 timer_pri_timeout_r(),
63 timer_pri_timeout_period_f(timeout_period) |
64 timer_pri_timeout_en_en_disabled_f());
65 }
66 gk20a_writel(g, bus_intr_en_0_r(), intr_en_mask);
67}
68
69void gk20a_bus_isr(struct gk20a *g)
70{
71 u32 val, save0, save1, fecs_errcode = 0;
72
73 val = gk20a_readl(g, bus_intr_0_r());
74
75 if (val & (bus_intr_0_pri_squash_m() |
76 bus_intr_0_pri_fecserr_m() |
77 bus_intr_0_pri_timeout_m())) {
78
79 nvgpu_log(g, gpu_dbg_intr, "pmc_enable : 0x%x",
80 gk20a_readl(g, mc_enable_r()));
81
82 save0 = gk20a_readl(g, timer_pri_timeout_save_0_r());
83 if (timer_pri_timeout_save_0_fecs_tgt_v(save0)) {
84 /*
85 * write & addr fields in timeout_save0
86 * might not be reliable
87 */
88 fecs_errcode = gk20a_readl(g,
89 timer_pri_timeout_fecs_errcode_r());
90 }
91
92 save1 = gk20a_readl(g, timer_pri_timeout_save_1_r());
93 nvgpu_err(g, "NV_PBUS_INTR_0: 0x%08x ADR 0x%08x "
94 "%s DATA 0x%08x ",
95 val,
96 timer_pri_timeout_save_0_addr_v(save0) << 2,
97 timer_pri_timeout_save_0_write_v(save0) ?
98 "WRITE" : "READ", save1);
99
100 gk20a_writel(g, timer_pri_timeout_save_0_r(), 0);
101 gk20a_writel(g, timer_pri_timeout_save_1_r(), 0);
102
103 if (fecs_errcode) {
104 nvgpu_err(g, "FECS_ERRCODE 0x%08x", fecs_errcode);
105 if (g->ops.priv_ring.decode_error_code)
106 g->ops.priv_ring.decode_error_code(g,
107 fecs_errcode);
108
109 if ((fecs_errcode & 0xffffff00) == 0xbadf1300)
110 nvgpu_err(g, "NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC: "
111 "0x%08x",
112 gk20a_readl(g, gr_gpc0_fs_gpc_r()));
113 }
114
115 } else {
116 nvgpu_err(g, "Unhandled NV_PBUS_INTR_0: 0x%08x", val);
117 }
118 gk20a_writel(g, bus_intr_0_r(), val);
119}
120
121int gk20a_read_ptimer(struct gk20a *g, u64 *value)
122{
123 const unsigned int max_iterations = 3;
124 unsigned int i = 0;
125 u32 gpu_timestamp_hi_prev = 0;
126
127 if (!value)
128 return -EINVAL;
129
130 /* Note. The GPU nanosecond timer consists of two 32-bit
131 * registers (high & low). To detect a possible low register
132 * wrap-around between the reads, we need to read the high
133 * register before and after low. The wraparound happens
134 * approximately once per 4 secs. */
135
136 /* get initial gpu_timestamp_hi value */
137 gpu_timestamp_hi_prev = gk20a_readl(g, timer_time_1_r());
138
139 for (i = 0; i < max_iterations; ++i) {
140 u32 gpu_timestamp_hi = 0;
141 u32 gpu_timestamp_lo = 0;
142
143 gpu_timestamp_lo = gk20a_readl(g, timer_time_0_r());
144 gpu_timestamp_hi = gk20a_readl(g, timer_time_1_r());
145
146 if (gpu_timestamp_hi == gpu_timestamp_hi_prev) {
147 *value = (((u64)gpu_timestamp_hi) << 32) |
148 gpu_timestamp_lo;
149 return 0;
150 }
151
152 /* wrap-around detected, retry */
153 gpu_timestamp_hi_prev = gpu_timestamp_hi;
154 }
155
156 /* too many iterations, bail out */
157 nvgpu_err(g, "failed to read ptimer");
158 return -EBUSY;
159}
160
161int gk20a_bus_bar1_bind(struct gk20a *g, struct nvgpu_mem *bar1_inst)
162{
163 u64 iova = nvgpu_inst_block_addr(g, bar1_inst);
164 u32 ptr_v = (u32)(iova >> bus_bar1_block_ptr_shift_v());
165
166 nvgpu_log(g, gpu_dbg_info, "bar1 inst block ptr: 0x%08x", ptr_v);
167
168 gk20a_writel(g, bus_bar1_block_r(),
169 nvgpu_aperture_mask(g, bar1_inst,
170 bus_bar1_block_target_sys_mem_ncoh_f(),
171 bus_bar1_block_target_sys_mem_coh_f(),
172 bus_bar1_block_target_vid_mem_f()) |
173 bus_bar1_block_mode_virtual_f() |
174 bus_bar1_block_ptr_f(ptr_v));
175
176 return 0;
177}
178
179void gk20a_bus_set_ppriv_timeout_settings(struct gk20a *g)
180{
181 /*
182 * Bug 1340570: increase the clock timeout to avoid potential
183 * operation failure at high gpcclk rate. Default values are 0x400.
184 */
185 nvgpu_writel(g, pri_ringstation_sys_master_config_r(0x15), 0x800);
186 nvgpu_writel(g, pri_ringstation_gpc_master_config_r(0xa), 0x800);
187 nvgpu_writel(g, pri_ringstation_fbp_master_config_r(0x8), 0x800);
188}
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-04 21:56:28 -0400