gpu: nvgpu: fix MISRA Rule 11.6 issue with fence pool mgmt

MISRA Rule 11.6 prohibits the casting of an integer value to a
void *.

The nvgpu allocator used for the fence pool stores the base
address of the associated memory as a u64 and returns it via
nvgpu_alloc_base().

In gk20a_free_fence_pool() this u64 value was cast to a void *
before being passed to nvgpu_vfree() (leading to the violation).

This change modifies gk20a_free_fence_pool() to cast the base
address back to the original struct gk20a_fence * to eliminate
the violation.

JIRA NVGPU-895: MISRA Rule 11.6 violations

Change-Id: If89cf2c1bc8ea4b0b59da4cf8b1c167738f6badc
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1774530
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

0 files changed, 0 insertions, 0 deletions