gpu: nvgpu: volt: fix MISRA Rule 10.4 Violations

MISRA Rule 10.4 only allows the usage of arithmetic operations on
operands of the same essential type category.

Adding "U" at the end of the integer literals to have same type of
operands when an arithmetic operation is performed.

This fixes violation where an arithmetic operation is performed on
signed and unsigned int types.

JIRA NVGPU-992

Change-Id: Ic9a911beb6d161df950ca85eb4813547603a8743
Signed-off-by: Sai Nikhil <snikhil@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1809751
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

2 files changed, 39 insertions, 39 deletions

diff --git a/drivers/gpu/nvgpu/ctrl/ctrlboardobj.h b/drivers/gpu/nvgpu/ctrl/ctrlboardobj.h
index 9e4402a5..8f57e880 100644
--- a/drivers/gpu/nvgpu/ctrl/ctrlboardobj.h
+++ b/drivers/gpu/nvgpu/ctrl/ctrlboardobj.h
@@ -27,20 +27,20 @@ struct ctrl_boardobj {
         u8    type;
 };
 
-#define CTRL_BOARDOBJGRP_TYPE_INVALID 0x00
-#define CTRL_BOARDOBJGRP_TYPE_E32 0x01
-#define CTRL_BOARDOBJGRP_TYPE_E255 0x02
+#define CTRL_BOARDOBJGRP_TYPE_INVALID                   0x00U
+#define CTRL_BOARDOBJGRP_TYPE_E32                       0x01U
+#define CTRL_BOARDOBJGRP_TYPE_E255                      0x02U
 
-#define CTRL_BOARDOBJGRP_E32_MAX_OBJECTS  32
+#define CTRL_BOARDOBJGRP_E32_MAX_OBJECTS                32U
 
-#define CTRL_BOARDOBJGRP_E255_MAX_OBJECTS 255
+#define CTRL_BOARDOBJGRP_E255_MAX_OBJECTS               255U
 
 #define CTRL_BOARDOBJ_MAX_BOARD_OBJECTS                                 \
         CTRL_BOARDOBJGRP_E32_MAX_OBJECTS
 
-#define CTRL_BOARDOBJ_IDX_INVALID 255
+#define CTRL_BOARDOBJ_IDX_INVALID                       255U
 
-#define CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_BIT_SIZE  32
+#define CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_BIT_SIZE     32U
 
 #define CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_INDEX(_bit)                  \
         ((_bit) / CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_BIT_SIZE)
@@ -49,10 +49,10 @@ struct ctrl_boardobj {
         ((_bit) % CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_BIT_SIZE)
 
 #define CTRL_BOARDOBJGRP_MASK_DATA_SIZE(_bits)                          \
-        (CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_INDEX((_bits) - 1) + 1)
+        (CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_INDEX((_bits) - 1U) + 1U)
 
 
-#define CTRL_BOARDOBJGRP_MASK_ARRAY_START_SIZE  1
+#define CTRL_BOARDOBJGRP_MASK_ARRAY_START_SIZE          1U
 #define CTRL_BOARDOBJGRP_MASK_ARRAY_EXTENSION_SIZE(_bits)          \
         (CTRL_BOARDOBJGRP_MASK_DATA_SIZE(_bits) -                           \
          CTRL_BOARDOBJGRP_MASK_ARRAY_START_SIZE)
diff --git a/drivers/gpu/nvgpu/ctrl/ctrlvolt.h b/drivers/gpu/nvgpu/ctrl/ctrlvolt.h
index ea06dbc4..84994eb6 100644
--- a/drivers/gpu/nvgpu/ctrl/ctrlvolt.h
+++ b/drivers/gpu/nvgpu/ctrl/ctrlvolt.h
@@ -30,25 +30,25 @@
 #include "ctrlperf.h"
 #include "ctrlboardobj.h"
 
-#define CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES   0x04
-#define CTRL_VOLT_VOLT_DEV_VID_VSEL_MAX_ENTRIES (8)
-#define CTRL_VOLT_DOMAIN_INVALID        0x00
-#define CTRL_VOLT_DOMAIN_LOGIC          0x01
-#define CLK_PROG_VFE_ENTRY_LOGIC        0x00
-#define CLK_PROG_VFE_ENTRY_SRAM 0x01
+#define CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES   0x04U
+#define CTRL_VOLT_VOLT_DEV_VID_VSEL_MAX_ENTRIES (8U)
+#define CTRL_VOLT_DOMAIN_INVALID                0x00U
+#define CTRL_VOLT_DOMAIN_LOGIC                  0x01U
+#define CLK_PROG_VFE_ENTRY_LOGIC                0x00U
+#define CLK_PROG_VFE_ENTRY_SRAM                 0x01U
 
 /*
  * Macros for Voltage Domain HAL.
  */
-#define CTRL_VOLT_DOMAIN_HAL_GP10X_SINGLE_RAIL 0x00
-#define CTRL_VOLT_DOMAIN_HAL_GP10X_SPLIT_RAIL  0x01
+#define CTRL_VOLT_DOMAIN_HAL_GP10X_SINGLE_RAIL 0x00U
+#define CTRL_VOLT_DOMAIN_HAL_GP10X_SPLIT_RAIL  0x01U
 
 /*
  * Macros for Voltage Domains.
  */
-#define CTRL_VOLT_DOMAIN_INVALID        0x00
-#define CTRL_VOLT_DOMAIN_LOGIC          0x01
-#define CTRL_VOLT_DOMAIN_SRAM           0x02
+#define CTRL_VOLT_DOMAIN_INVALID        0x00U
+#define CTRL_VOLT_DOMAIN_LOGIC          0x01U
+#define CTRL_VOLT_DOMAIN_SRAM           0x02U
 
 /*!
  * Special value corresponding to an invalid Voltage Rail Index.
@@ -79,43 +79,43 @@ enum nv_pmu_pmgr_pwm_source {
 /*!
  * Macros for Voltage Device Types.
  */
-#define CTRL_VOLT_DEVICE_TYPE_INVALID           0x00
-#define CTRL_VOLT_DEVICE_TYPE_PWM               0x03
+#define CTRL_VOLT_DEVICE_TYPE_INVALID           0x00U
+#define CTRL_VOLT_DEVICE_TYPE_PWM               0x03U
 
 /*
  * Macros for Volt Device Operation types.
  */
-#define CTRL_VOLT_DEVICE_OPERATION_TYPE_INVALID 0x00
-#define CTRL_VOLT_DEVICE_OPERATION_TYPE_DEFAULT 0x01
-#define CTRL_VOLT_DEVICE_OPERATION_TYPE_LPWR_STEADY_STATE       0x02
-#define CTRL_VOLT_DEVICE_OPERATION_TYPE_LPWR_SLEEP_STATE        0x03
-#define CTRL_VOLT_VOLT_DEVICE_OPERATION_TYPE_IPC_VMIN   0x04
+#define CTRL_VOLT_DEVICE_OPERATION_TYPE_INVALID                 0x00U
+#define CTRL_VOLT_DEVICE_OPERATION_TYPE_DEFAULT                 0x01U
+#define CTRL_VOLT_DEVICE_OPERATION_TYPE_LPWR_STEADY_STATE       0x02U
+#define CTRL_VOLT_DEVICE_OPERATION_TYPE_LPWR_SLEEP_STATE        0x03U
+#define CTRL_VOLT_VOLT_DEVICE_OPERATION_TYPE_IPC_VMIN           0x04U
 
 /*!
  * Macros for Voltage Domains.
  */
-#define CTRL_VOLT_DOMAIN_INVALID        0x00
-#define CTRL_VOLT_DOMAIN_LOGIC          0x01
-#define CTRL_VOLT_DOMAIN_SRAM           0x02
+#define CTRL_VOLT_DOMAIN_INVALID        0x00U
+#define CTRL_VOLT_DOMAIN_LOGIC          0x01U
+#define CTRL_VOLT_DOMAIN_SRAM           0x02U
 
 /*!
  * Macros for Volt Policy types.
  *
  * Virtual VOLT_POLICY types are indexed starting from 0xFF.
  */
-#define CTRL_VOLT_POLICY_TYPE_INVALID           0x00
-#define CTRL_VOLT_POLICY_TYPE_SINGLE_RAIL       0x01
-#define CTRL_VOLT_POLICY_TYPE_SR_MULTI_STEP     0x02
-#define CTRL_VOLT_POLICY_TYPE_SR_SINGLE_STEP    0x03
-#define CTRL_VOLT_POLICY_TYPE_SINGLE_RAIL_MULTI_STEP    0x04
-#define CTRL_VOLT_POLICY_TYPE_SPLIT_RAIL        0xFE
-#define CTRL_VOLT_POLICY_TYPE_UNKNOWN           0xFF
+#define CTRL_VOLT_POLICY_TYPE_INVALID                   0x00U
+#define CTRL_VOLT_POLICY_TYPE_SINGLE_RAIL               0x01U
+#define CTRL_VOLT_POLICY_TYPE_SR_MULTI_STEP             0x02U
+#define CTRL_VOLT_POLICY_TYPE_SR_SINGLE_STEP            0x03U
+#define CTRL_VOLT_POLICY_TYPE_SINGLE_RAIL_MULTI_STEP    0x04U
+#define CTRL_VOLT_POLICY_TYPE_SPLIT_RAIL                0xFEU
+#define CTRL_VOLT_POLICY_TYPE_UNKNOWN                   0xFFU
 
 /*!
  * Macros for Volt Policy Client types.
  */
-#define CTRL_VOLT_POLICY_CLIENT_INVALID                 0x00
-#define CTRL_VOLT_POLICY_CLIENT_PERF_CORE_VF_SEQ        0x01
+#define CTRL_VOLT_POLICY_CLIENT_INVALID                 0x00U
+#define CTRL_VOLT_POLICY_CLIENT_PERF_CORE_VF_SEQ        0x01U
 
 struct ctrl_volt_volt_rail_list_item {
         u8 rail_idx;