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| author | Deepak Nibade <dnibade@nvidia.com> | 2018-03-16 08:25:18 -0400 |
|---|---|---|
| committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-03-21 09:04:38 -0400 |
| commit | 77b806fe7e68e853676f7c4bad14349aba1affa5 (patch) | |
| tree | 2b0933a730d8b7f5144e0d51dfc89e3cb19a28f0 /drivers/gpu/nvgpu/ctrl | |
| parent | 66751bc05d7a1efca3668d59a2820e3e92985f91 (diff) | |
gpu: nvgpu: gv100: fix PMA list alignment in ctxsw buffer
GV100 ucode is changed so that it expects LIST_nv_perf_pma_ctx_reg list in
ctxsw buffer to be 256 byte aligned but same change is not applied to other
chip ucodes
ADD new HAL (*add_ctxsw_reg_perf_pma) to configure PMA register list and
define a common HAL gr_gk20a_add_ctxsw_reg_perf_pma() for all other
chips except GV100
Define a separate HAL for GV100 gr_gv100_add_ctxsw_reg_perf_pma() and fix
the required alignment in this function
Bug 1998067
Change-Id: Ie172fe90e2cdbac2509f2ece953cd8552e66fc56
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1676655
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/ctrl')
0 files changed, 0 insertions, 0 deletions