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authorTejal Kudav <tkudav@nvidia.com>2017-11-08 04:56:23 -0500
committermobile promotions <svcmobile_promotions@nvidia.com>2018-04-12 05:31:15 -0400
commit2114869a4084809be18a489dc44d1b8f28e66598 (patch)
treebeb0b902d0c1424a9086a3d0f6ba04dfaebf13d0 /drivers/gpu/nvgpu/ctrl
parent1f4bbff6e068e4b718b69bea5b9a1c3c07f5c49a (diff)
gpu: nvgpu: Update clk_fll interface as per chips_a
Two new members added to fll struct and code modified to support GV100 VBIOS NAFLL tables Add g->ops for getting vbios clk domains JIRA NVGPUGV100-39 Change-Id: Iaabea893d55d44a272e2bce2b1d525b122cd36f5 Signed-off-by: Tejal Kudav <tkudav@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1594289 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com> Tested-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/ctrl')
-rw-r--r--drivers/gpu/nvgpu/ctrl/ctrlclkavfs.h7
1 files changed, 5 insertions, 2 deletions
diff --git a/drivers/gpu/nvgpu/ctrl/ctrlclkavfs.h b/drivers/gpu/nvgpu/ctrl/ctrlclkavfs.h
index cfc6538a..59a542c8 100644
--- a/drivers/gpu/nvgpu/ctrl/ctrlclkavfs.h
+++ b/drivers/gpu/nvgpu/ctrl/ctrlclkavfs.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a 4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"), 5 * copy of this software and associated documentation files (the "Software"),
@@ -79,7 +79,7 @@
79 BIT(CTRL_CLK_FLL_ID_GPC4) | \ 79 BIT(CTRL_CLK_FLL_ID_GPC4) | \
80 BIT(CTRL_CLK_FLL_ID_GPC5)) 80 BIT(CTRL_CLK_FLL_ID_GPC5))
81/*! 81/*!
82 * Mask of all FLL IDs supported by RM 82 * Mask of all FLL IDs supported by Nvgpu driver
83 */ 83 */
84#define CTRL_CLK_FLL_ID_ALL_MASK (BIT(CTRL_CLK_FLL_ID_SYS) | \ 84#define CTRL_CLK_FLL_ID_ALL_MASK (BIT(CTRL_CLK_FLL_ID_SYS) | \
85 BIT(CTRL_CLK_FLL_ID_LTC) | \ 85 BIT(CTRL_CLK_FLL_ID_LTC) | \
@@ -96,4 +96,7 @@
96#define CTRL_CLK_FLL_REGIME_ID_FFR (0x00000001) 96#define CTRL_CLK_FLL_REGIME_ID_FFR (0x00000001)
97#define CTRL_CLK_FLL_REGIME_ID_FR (0x00000002) 97#define CTRL_CLK_FLL_REGIME_ID_FR (0x00000002)
98 98
99#define CTRL_CLK_FLL_LUT_VSELECT_LOGIC (0x00000000)
100#define CTRL_CLK_FLL_LUT_VSELECT_MIN (0x00000001)
101#define CTRL_CLK_FLL_LUT_VSELECT_SRAM (0x00000002)
99#endif 102#endif