summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/nvgpu/ctrl/ctrlvolt.h
diff options
context:
space:
mode:
authorMahantesh Kumbar <mkumbar@nvidia.com>2018-02-14 04:01:01 -0500
committermobile promotions <svcmobile_promotions@nvidia.com>2018-03-15 02:46:59 -0400
commitd3f96dfa96a8aafe6f5035e2ed24425141e4202e (patch)
tree05eb958518d5e6d9f31d607d1a9cf2f6e39ce295 /drivers/gpu/nvgpu/ctrl/ctrlvolt.h
parente77ec1a98e6d65eac5b56999af17d51ffca6671f (diff)
gpu: nvgpu: gv10x volt rail boardobj changes
- Created volt ops under pmu_ver to support volt_set_voltage, volt_get_voltage & volt_send_load_cmd_to_pmu. - Renamed volt load, set_voltage & get_voltage gp10x method names. - Added new volt load, set_voltage & get_voltage methods for gv10x using RPC & added code to handle ack in pmu_rpc_handler() along with struct rail_list changes. - Updated volt ops of gp106 & gv100 to point to respective methods. - Added member volt_dev_idx_ipc_vmin & volt_scale_exp_pwr_equ_idx to "struct nv_pmu_volt_volt_rail_boardobj_set" & "struct voltage_rail" made changes to update members as needed. - Added member volt_scale_exp_pwr_equ_idx to "struct vbios_voltage_rail_table_1x_entry" to read value from VBIOS table & update rail boardobj set interface. - Defines for volt RPC "NV_PMU_RPC_ID_VOLT_*" - Define struct's volt load, set_voltage & get_voltage to execute volt RPC. Change-Id: I4a41adcf7536468beaa8a73f551b1d608aabd161 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1659728 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/ctrl/ctrlvolt.h')
-rw-r--r--drivers/gpu/nvgpu/ctrl/ctrlvolt.h15
1 files changed, 14 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/ctrl/ctrlvolt.h b/drivers/gpu/nvgpu/ctrl/ctrlvolt.h
index c99aa79f..1a82fbed 100644
--- a/drivers/gpu/nvgpu/ctrl/ctrlvolt.h
+++ b/drivers/gpu/nvgpu/ctrl/ctrlvolt.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * general p state infrastructure 2 * general p state infrastructure
3 * 3 *
4 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. 4 * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
5 * 5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a 6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"), 7 * copy of this software and associated documentation files (the "Software"),
@@ -89,6 +89,7 @@ enum nv_pmu_pmgr_pwm_source {
89#define CTRL_VOLT_DEVICE_OPERATION_TYPE_DEFAULT 0x01 89#define CTRL_VOLT_DEVICE_OPERATION_TYPE_DEFAULT 0x01
90#define CTRL_VOLT_DEVICE_OPERATION_TYPE_LPWR_STEADY_STATE 0x02 90#define CTRL_VOLT_DEVICE_OPERATION_TYPE_LPWR_STEADY_STATE 0x02
91#define CTRL_VOLT_DEVICE_OPERATION_TYPE_LPWR_SLEEP_STATE 0x03 91#define CTRL_VOLT_DEVICE_OPERATION_TYPE_LPWR_SLEEP_STATE 0x03
92#define CTRL_VOLT_VOLT_DEVICE_OPERATION_TYPE_IPC_VMIN 0x04
92 93
93/*! 94/*!
94 * Macros for Voltage Domains. 95 * Macros for Voltage Domains.
@@ -126,4 +127,16 @@ struct ctrl_volt_volt_rail_list {
126 rails[CTRL_VOLT_VOLT_RAIL_MAX_RAILS]; 127 rails[CTRL_VOLT_VOLT_RAIL_MAX_RAILS];
127}; 128};
128 129
130struct ctrl_volt_volt_rail_list_item_v1 {
131 u8 rail_idx;
132 u32 voltage_uv;
133 u32 voltage_min_noise_unaware_uv;
134};
135
136struct ctrl_volt_volt_rail_list_v1 {
137 u8 num_rails;
138 struct ctrl_volt_volt_rail_list_item_v1
139 rails[CTRL_VOLT_VOLT_RAIL_MAX_RAILS];
140};
141
129#endif 142#endif