gpu: nvgpu: pmgr: fix MISRA Rule 10.4 Violations

MISRA Rule 10.4 only allows the usage of arithmetic operations on
operands of the same essential type category.

Adding "U" at the end of the integer literals to have same type of
operands when an arithmetic operation is performed.

This fixes violation where an arithmetic operation is performed on
signed and unsigned int types.

JIRA NVGPU-992

Change-Id: Id3b2c8ea1af1807087468c6978abfbfc85bee2ec
Signed-off-by: Sai Nikhil <snikhil@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1809757
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 13 insertions, 13 deletions

diff --git a/drivers/gpu/nvgpu/ctrl/ctrlpmgr.h b/drivers/gpu/nvgpu/ctrl/ctrlpmgr.h
index 165bbd5d..90f6501b 100644
--- a/drivers/gpu/nvgpu/ctrl/ctrlpmgr.h
+++ b/drivers/gpu/nvgpu/ctrl/ctrlpmgr.h
@@ -27,23 +27,23 @@
 #include "ctrlboardobj.h"
 
 /* valid power domain values */
-#define CTRL_PMGR_PWR_DEVICES_MAX_DEVICES 32
-#define CTRL_PMGR_PWR_VIOLATION_MAX 0x06
+#define CTRL_PMGR_PWR_DEVICES_MAX_DEVICES                       32U
+#define CTRL_PMGR_PWR_VIOLATION_MAX                             0x06U
 
-#define CTRL_PMGR_PWR_DEVICE_TYPE_INA3221                            0x4E
+#define CTRL_PMGR_PWR_DEVICE_TYPE_INA3221                       0x4EU
 
-#define CTRL_PMGR_PWR_CHANNEL_INDEX_INVALID                          0xFF
-#define CTRL_PMGR_PWR_CHANNEL_TYPE_SENSOR                            0x08
+#define CTRL_PMGR_PWR_CHANNEL_INDEX_INVALID                     0xFFU
+#define CTRL_PMGR_PWR_CHANNEL_TYPE_SENSOR                       0x08U
 
-#define CTRL_PMGR_PWR_POLICY_TABLE_VERSION_3X                        0x30
-#define CTRL_PMGR_PWR_POLICY_TYPE_HW_THRESHOLD                       0x04
-#define CTRL_PMGR_PWR_POLICY_TYPE_SW_THRESHOLD                       0x0C
+#define CTRL_PMGR_PWR_POLICY_TABLE_VERSION_3X                   0x30U
+#define CTRL_PMGR_PWR_POLICY_TYPE_HW_THRESHOLD                  0x04U
+#define CTRL_PMGR_PWR_POLICY_TYPE_SW_THRESHOLD                  0x0CU
 
-#define CTRL_PMGR_PWR_POLICY_MAX_LIMIT_INPUTS                       0x8
-#define CTRL_PMGR_PWR_POLICY_IDX_NUM_INDEXES                         0x08
-#define CTRL_PMGR_PWR_POLICY_INDEX_INVALID                           0xFF
-#define CTRL_PMGR_PWR_POLICY_LIMIT_INPUT_CLIENT_IDX_RM                 0xFE
-#define CTRL_PMGR_PWR_POLICY_LIMIT_MAX                       (0xFFFFFFFF)
+#define CTRL_PMGR_PWR_POLICY_MAX_LIMIT_INPUTS                   0x8U
+#define CTRL_PMGR_PWR_POLICY_IDX_NUM_INDEXES                    0x08U
+#define CTRL_PMGR_PWR_POLICY_INDEX_INVALID                      0xFFU
+#define CTRL_PMGR_PWR_POLICY_LIMIT_INPUT_CLIENT_IDX_RM          0xFEU
+#define CTRL_PMGR_PWR_POLICY_LIMIT_MAX                          (0xFFFFFFFFU)
 
 struct ctrl_pmgr_pwr_device_info_rshunt {
         bool use_fxp8_8;