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author | David Nieto <dmartineznie@nvidia.com> | 2017-03-22 19:57:56 -0400 |
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committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-03-23 23:34:50 -0400 |
commit | ab401c70682c98adae6f3c5c7225fdc8e1294fc7 (patch) | |
tree | 7cd1344ee97b628cf347c96a9f20dfa5fd371214 /drivers/gpu/nvgpu/ctrl/ctrlpmgr.h | |
parent | fb71b882750332fde543550adffe3f70f1d47d47 (diff) |
gpu: nvgpu: fix running condition on fifo isr
The fifo interrupt path was reading the PBDMA interrupt status
after clearing interrupts and this could lead to a situation in
which the host may have advanced to another channel, leading to
the recovery code resetting the wrong channel.
Bug 200278729
JIRA: EVLR-1036
Change-Id: I392423d1eaa8d23acf88454bf113c015e649e13d
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1326461
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/ctrl/ctrlpmgr.h')
0 files changed, 0 insertions, 0 deletions