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authorsmadhavan <smadhavan@nvidia.com>2018-09-11 01:26:57 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-09-18 02:40:03 -0400
commitde6b40b862d0a0c43d1b93d28c8a705040ebd4a3 (patch)
tree54bc8666488238a412608d865313cc07f9d06eeb /drivers/gpu/nvgpu/ctrl/ctrlperf.h
parent82c94e22916fb76fbb145e88079130ed4c6a6c32 (diff)
nvgpu: ctrl: MISRA Rule 21.2 header guard fixes
MISRA rule 21.2 doesn't allow the use of macro names which start with an underscore. These leading underscores are to be removed from the macro names. This patch will fix such violations in ctrl by renaming them to follow the convention, 'NVGPU_PARENT-DIR_HEADER-NAME' when there is no keyword repetition between file name and directory or 'NVGPU_HEADER-NAME' when there is repetition. JIRA NVGPU-1028 Change-Id: Ia7e5bf76dd2a8689e365bdeb27eac4b6e9ca4cfd Signed-off-by: smadhavan <smadhavan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1815657 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Adeel Raza <araza@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/ctrl/ctrlperf.h')
-rw-r--r--drivers/gpu/nvgpu/ctrl/ctrlperf.h6
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/ctrl/ctrlperf.h b/drivers/gpu/nvgpu/ctrl/ctrlperf.h
index 477b33d8..2928cad1 100644
--- a/drivers/gpu/nvgpu/ctrl/ctrlperf.h
+++ b/drivers/gpu/nvgpu/ctrl/ctrlperf.h
@@ -21,8 +21,8 @@
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE. 22 * DEALINGS IN THE SOFTWARE.
23 */ 23 */
24#ifndef _ctrlperf_h_ 24#ifndef NVGPU_CTRLPERF_H
25#define _ctrlperf_h_ 25#define NVGPU_CTRLPERF_H
26 26
27struct ctrl_perf_volt_rail_list_item { 27struct ctrl_perf_volt_rail_list_item {
28 u8 volt_domain; 28 u8 volt_domain;
@@ -100,4 +100,4 @@ struct ctrl_perf_vfe_var_single_sensed_fuse_ver_vfield_info {
100 bool b_use_default_on_ver_check_fail; 100 bool b_use_default_on_ver_check_fail;
101 u8 v_field_id_ver; 101 u8 v_field_id_ver;
102}; 102};
103#endif 103#endif /* NVGPU_CTRLPERF_H */