gpu: nvgpu: Add dGPU clocks support

JIRA DNVGPU-45

Change-Id: I237ce81e31b036c05c82d46eea8694ffe1c2e3df
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Signed-off-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/1205849
(cherry picked from commit 9a4006f76b75a8ad525e7aa5ad1f609aaae49126)
Reviewed-on: http://git-master/r/1227256
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 32 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/ctrl/ctrlperf.h b/drivers/gpu/nvgpu/ctrl/ctrlperf.h
new file mode 100644
index 00000000..89697dfd
--- /dev/null
+++ b/drivers/gpu/nvgpu/ctrl/ctrlperf.h
@@ -0,0 +1,32 @@
+/*
+ * general p state infrastructure
+ *
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+#ifndef _ctrlperf_h_
+#define _ctrlperf_h_
+
+#include "ctrlvolt.h"
+
+struct ctrl_perf_volt_rail_list_item {
+        u8 volt_domain;
+        u32 voltage_uv;
+        u32 voltage_min_noise_unaware_uv;
+};
+
+struct ctrl_perf_volt_rail_list {
+        u8    num_rails;
+        struct ctrl_perf_volt_rail_list_item
+                rails[CTRL_VOLT_VOLT_RAIL_MAX_RAILS];
+};
+
+#endif