gpu: nvgpu: Update vfe_var interface as per chips_a_23609936

Changes made:
1. Fuse value can now be signed or unsigned. A new boolean added to check
if the value is signed or not.
2. Masks added for dependent variable and equations
3. Restructing some data structures as per r384

JIRA NVGPUGV100-39

Change-Id: I7d9d1a55e26a06686f6253dedeb55925a32fd0ad
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1597761
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vaikundanathan S <vaikuns@nvidia.com>
Tested-by: Vaikundanathan S <vaikuns@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 65 insertions, 1 deletions

diff --git a/drivers/gpu/nvgpu/ctrl/ctrlperf.h b/drivers/gpu/nvgpu/ctrl/ctrlperf.h
index 52ff60c7..477b33d8 100644
--- a/drivers/gpu/nvgpu/ctrl/ctrlperf.h
+++ b/drivers/gpu/nvgpu/ctrl/ctrlperf.h
@@ -1,7 +1,7 @@
 /*
  * general p state infrastructure
  *
- * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -36,4 +36,68 @@ struct ctrl_perf_volt_rail_list {
                 rails[CTRL_VOLT_VOLT_RAIL_MAX_RAILS];
 };
 
+union ctrl_perf_vfe_var_single_sensed_fuse_value_data {
+        int signed_value;
+        u32 unsigned_value;
+};
+
+struct ctrl_perf_vfe_var_single_sensed_fuse_value {
+        bool b_signed;
+        union ctrl_perf_vfe_var_single_sensed_fuse_value_data data;
+};
+
+struct ctrl_bios_vfield_register_segment_super {
+        u8 low_bit;
+        u8 high_bit;
+};
+
+struct ctrl_bios_vfield_register_segment_reg {
+        struct ctrl_bios_vfield_register_segment_super super;
+        u32 addr;
+};
+
+struct ctrl_bios_vfield_register_segment_index_reg {
+        struct ctrl_bios_vfield_register_segment_super super;
+        u32 addr;
+        u32 reg_index;
+        u32 index;
+};
+
+union ctrl_bios_vfield_register_segment_data {
+        struct ctrl_bios_vfield_register_segment_reg reg;
+        struct ctrl_bios_vfield_register_segment_index_reg index_reg;
+};
+
+struct ctrl_bios_vfield_register_segment {
+        u8 type;
+        union ctrl_bios_vfield_register_segment_data data;
+};
+
+#define NV_PMU_VFE_VAR_SINGLE_SENSED_FUSE_SEGMENTS_MAX                         1
+
+struct ctrl_perf_vfe_var_single_sensed_fuse_info {
+        u8 segment_count;
+        struct ctrl_bios_vfield_register_segment segments[NV_PMU_VFE_VAR_SINGLE_SENSED_FUSE_SEGMENTS_MAX];
+};
+
+struct ctrl_perf_vfe_var_single_sensed_fuse_override_info {
+        u32 fuse_val_override;
+        u8 b_fuse_regkey_override;
+};
+
+struct ctrl_perf_vfe_var_single_sensed_fuse_vfield_info {
+        struct ctrl_perf_vfe_var_single_sensed_fuse_info fuse;
+        u32 fuse_val_default;
+        u32 hw_correction_scale;
+        int hw_correction_offset;
+        u8 v_field_id;
+};
+
+struct ctrl_perf_vfe_var_single_sensed_fuse_ver_vfield_info {
+        struct ctrl_perf_vfe_var_single_sensed_fuse_info fuse;
+        u8 ver_expected;
+        bool b_ver_check;
+        bool b_use_default_on_ver_check_fail;
+        u8 v_field_id_ver;
+};
 #endif