diff options
author | Vijayakumar Subbu <vsubbu@nvidia.com> | 2016-07-28 01:29:15 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2016-09-29 16:17:46 -0400 |
commit | b17d9708c9e9930778de43de1edf1385acb13ebd (patch) | |
tree | fc485e96cc19575d463c61c8b80a09dd89745f3f /drivers/gpu/nvgpu/ctrl/ctrlclkavfs.h | |
parent | 27b47b1969d7d9cdd3de9fd6f0131ad357f4b0fa (diff) |
gpu: nvgpu: Add dGPU clocks support
JIRA DNVGPU-45
Change-Id: I237ce81e31b036c05c82d46eea8694ffe1c2e3df
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Signed-off-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/1205849
(cherry picked from commit 9a4006f76b75a8ad525e7aa5ad1f609aaae49126)
Reviewed-on: http://git-master/r/1227256
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/ctrl/ctrlclkavfs.h')
-rw-r--r-- | drivers/gpu/nvgpu/ctrl/ctrlclkavfs.h | 88 |
1 files changed, 88 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/ctrl/ctrlclkavfs.h b/drivers/gpu/nvgpu/ctrl/ctrlclkavfs.h new file mode 100644 index 00000000..7e28a5d9 --- /dev/null +++ b/drivers/gpu/nvgpu/ctrl/ctrlclkavfs.h | |||
@@ -0,0 +1,88 @@ | |||
1 | /* | ||
2 | * _NVRM_COPYRIGHT_BEGIN_ | ||
3 | * | ||
4 | * Copyright 2015-2016 by NVIDIA Corporation. All rights reserved. All | ||
5 | * information contained herein is proprietary and confidential to NVIDIA | ||
6 | * Corporation. Any use, reproduction, or disclosure without the written | ||
7 | * permission of NVIDIA Corporation is prohibited. | ||
8 | * | ||
9 | * _NVRM_COPYRIGHT_END_ | ||
10 | */ | ||
11 | |||
12 | #ifndef _ctrlclkavfs_h_ | ||
13 | #define _ctrlclkavfs_h_ | ||
14 | |||
15 | #include "ctrlboardobj.h" | ||
16 | /*! | ||
17 | * Valid global VIN ID values | ||
18 | */ | ||
19 | #define CTRL_CLK_VIN_ID_SYS 0x00000000 | ||
20 | #define CTRL_CLK_VIN_ID_LTC 0x00000001 | ||
21 | #define CTRL_CLK_VIN_ID_XBAR 0x00000002 | ||
22 | #define CTRL_CLK_VIN_ID_GPC0 0x00000003 | ||
23 | #define CTRL_CLK_VIN_ID_GPC1 0x00000004 | ||
24 | #define CTRL_CLK_VIN_ID_GPC2 0x00000005 | ||
25 | #define CTRL_CLK_VIN_ID_GPC3 0x00000006 | ||
26 | #define CTRL_CLK_VIN_ID_GPC4 0x00000007 | ||
27 | #define CTRL_CLK_VIN_ID_GPC5 0x00000008 | ||
28 | #define CTRL_CLK_VIN_ID_GPCS 0x00000009 | ||
29 | #define CTRL_CLK_VIN_ID_SRAM 0x0000000A | ||
30 | #define CTRL_CLK_VIN_ID_UNDEFINED 0x000000FF | ||
31 | |||
32 | #define CTRL_CLK_VIN_TYPE_DISABLED 0x00000000 | ||
33 | |||
34 | /*! | ||
35 | * Mask of all GPC VIN IDs supported by RM | ||
36 | */ | ||
37 | #define CTRL_CLK_VIN_MASK_UNICAST_GPC (BIT(CTRL_CLK_VIN_ID_GPC0) | \ | ||
38 | BIT(CTRL_CLK_VIN_ID_GPC1) | \ | ||
39 | BIT(CTRL_CLK_VIN_ID_GPC2) | \ | ||
40 | BIT(CTRL_CLK_VIN_ID_GPC3) | \ | ||
41 | BIT(CTRL_CLK_VIN_ID_GPC4) | \ | ||
42 | BIT(CTRL_CLK_VIN_ID_GPC5)) | ||
43 | #define CTRL_CLK_LUT_NUM_ENTRIES 0x50 | ||
44 | #define CTRL_CLK_VIN_STEP_SIZE_UV (10000) | ||
45 | #define CTRL_CLK_LUT_MIN_VOLTAGE_UV (450000) | ||
46 | #define CTRL_CLK_FLL_TYPE_DISABLED 0 | ||
47 | |||
48 | #define CTRL_CLK_FLL_ID_SYS (0x00000000) | ||
49 | #define CTRL_CLK_FLL_ID_LTC (0x00000001) | ||
50 | #define CTRL_CLK_FLL_ID_XBAR (0x00000002) | ||
51 | #define CTRL_CLK_FLL_ID_GPC0 (0x00000003) | ||
52 | #define CTRL_CLK_FLL_ID_GPC1 (0x00000004) | ||
53 | #define CTRL_CLK_FLL_ID_GPC2 (0x00000005) | ||
54 | #define CTRL_CLK_FLL_ID_GPC3 (0x00000006) | ||
55 | #define CTRL_CLK_FLL_ID_GPC4 (0x00000007) | ||
56 | #define CTRL_CLK_FLL_ID_GPC5 (0x00000008) | ||
57 | #define CTRL_CLK_FLL_ID_GPCS (0x00000009) | ||
58 | #define CTRL_CLK_FLL_ID_UNDEFINED (0x000000FF) | ||
59 | #define CTRL_CLK_FLL_MASK_UNDEFINED (0x00000000) | ||
60 | |||
61 | /*! | ||
62 | * Mask of all GPC FLL IDs supported by RM | ||
63 | */ | ||
64 | #define CTRL_CLK_FLL_MASK_UNICAST_GPC (BIT(CTRL_CLK_FLL_ID_GPC0) | \ | ||
65 | BIT(CTRL_CLK_FLL_ID_GPC1) | \ | ||
66 | BIT(CTRL_CLK_FLL_ID_GPC2) | \ | ||
67 | BIT(CTRL_CLK_FLL_ID_GPC3) | \ | ||
68 | BIT(CTRL_CLK_FLL_ID_GPC4) | \ | ||
69 | BIT(CTRL_CLK_FLL_ID_GPC5)) | ||
70 | /*! | ||
71 | * Mask of all FLL IDs supported by RM | ||
72 | */ | ||
73 | #define CTRL_CLK_FLL_ID_ALL_MASK (BIT(CTRL_CLK_FLL_ID_SYS) | \ | ||
74 | BIT(CTRL_CLK_FLL_ID_LTC) | \ | ||
75 | BIT(CTRL_CLK_FLL_ID_XBAR) | \ | ||
76 | BIT(CTRL_CLK_FLL_ID_GPC0) | \ | ||
77 | BIT(CTRL_CLK_FLL_ID_GPC1) | \ | ||
78 | BIT(CTRL_CLK_FLL_ID_GPC2) | \ | ||
79 | BIT(CTRL_CLK_FLL_ID_GPC3) | \ | ||
80 | BIT(CTRL_CLK_FLL_ID_GPC4) | \ | ||
81 | BIT(CTRL_CLK_FLL_ID_GPC5) | \ | ||
82 | BIT(CTRL_CLK_FLL_ID_GPCS)) | ||
83 | |||
84 | #define CTRL_CLK_FLL_REGIME_ID_INVALID (0x00000000) | ||
85 | #define CTRL_CLK_FLL_REGIME_ID_FFR (0x00000001) | ||
86 | #define CTRL_CLK_FLL_REGIME_ID_FR (0x00000002) | ||
87 | |||
88 | #endif | ||