diff options
author | Vijayakumar Subbu <vsubbu@nvidia.com> | 2016-07-28 01:29:15 -0400 |
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committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2016-09-29 16:17:46 -0400 |
commit | b17d9708c9e9930778de43de1edf1385acb13ebd (patch) | |
tree | fc485e96cc19575d463c61c8b80a09dd89745f3f /drivers/gpu/nvgpu/ctrl/ctrlclk.h | |
parent | 27b47b1969d7d9cdd3de9fd6f0131ad357f4b0fa (diff) |
gpu: nvgpu: Add dGPU clocks support
JIRA DNVGPU-45
Change-Id: I237ce81e31b036c05c82d46eea8694ffe1c2e3df
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Signed-off-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/1205849
(cherry picked from commit 9a4006f76b75a8ad525e7aa5ad1f609aaae49126)
Reviewed-on: http://git-master/r/1227256
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/ctrl/ctrlclk.h')
-rw-r--r-- | drivers/gpu/nvgpu/ctrl/ctrlclk.h | 153 |
1 files changed, 153 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/ctrl/ctrlclk.h b/drivers/gpu/nvgpu/ctrl/ctrlclk.h new file mode 100644 index 00000000..76054d27 --- /dev/null +++ b/drivers/gpu/nvgpu/ctrl/ctrlclk.h | |||
@@ -0,0 +1,153 @@ | |||
1 | /* | ||
2 | * general p state infrastructure | ||
3 | * | ||
4 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms and conditions of the GNU General Public License, | ||
8 | * version 2, as published by the Free Software Foundation. | ||
9 | * | ||
10 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
13 | * more details. | ||
14 | */ | ||
15 | #ifndef _ctrlclk_h_ | ||
16 | #define _ctrlclk_h_ | ||
17 | |||
18 | #include "ctrlboardobj.h" | ||
19 | #include "ctrlclkavfs.h" | ||
20 | #include "ctrlvolt.h" | ||
21 | |||
22 | #define CTRL_CLK_CLK_DELTA_MAX_VOLT_RAILS 4 | ||
23 | |||
24 | /* valid clock domain values */ | ||
25 | #define CTRL_CLK_DOMAIN_MCLK (0x00000010) | ||
26 | #define CTRL_CLK_DOMAIN_DISPCLK (0x00000040) | ||
27 | #define CTRL_CLK_DOMAIN_GPC2CLK (0x00010000) | ||
28 | #define CTRL_CLK_DOMAIN_XBAR2CLK (0x00040000) | ||
29 | #define CTRL_CLK_DOMAIN_SYS2CLK (0x00080000) | ||
30 | #define CTRL_CLK_DOMAIN_HUB2CLK (0x00100000) | ||
31 | #define CTRL_CLK_DOMAIN_PWRCLK (0x00800000) | ||
32 | #define CTRL_CLK_DOMAIN_NVDCLK (0x01000000) | ||
33 | #define CTRL_CLK_DOMAIN_PCIEGENCLK (0x02000000) | ||
34 | |||
35 | #define CTRL_CLK_DOMAIN_GPCCLK (0x10000000) | ||
36 | #define CTRL_CLK_DOMAIN_XBARCLK (0x20000000) | ||
37 | #define CTRL_CLK_DOMAIN_SYSCLK (0x40000000) | ||
38 | #define CTRL_CLK_DOMAIN_HUBCLK (0x80000000) | ||
39 | |||
40 | #define CTRL_CLK_CLK_DOMAIN_TYPE_3X 0x01 | ||
41 | #define CTRL_CLK_CLK_DOMAIN_TYPE_3X_FIXED 0x02 | ||
42 | #define CTRL_CLK_CLK_DOMAIN_TYPE_3X_PROG 0x03 | ||
43 | #define CTRL_CLK_CLK_DOMAIN_TYPE_3X_MASTER 0x04 | ||
44 | #define CTRL_CLK_CLK_DOMAIN_TYPE_3X_SLAVE 0x05 | ||
45 | |||
46 | #define CTRL_CLK_CLK_DOMAIN_3X_PROG_ORDERING_INDEX_INVALID 0xFF | ||
47 | #define CTRL_CLK_CLK_DOMAIN_INDEX_INVALID 0xFF | ||
48 | |||
49 | #define CTRL_CLK_CLK_PROG_TYPE_1X 0x00 | ||
50 | #define CTRL_CLK_CLK_PROG_TYPE_1X_MASTER 0x01 | ||
51 | #define CTRL_CLK_CLK_PROG_TYPE_1X_MASTER_RATIO 0x02 | ||
52 | #define CTRL_CLK_CLK_PROG_TYPE_1X_MASTER_TABLE 0x03 | ||
53 | #define CTRL_CLK_CLK_PROG_TYPE_UNKNOWN 255 | ||
54 | |||
55 | /*! | ||
56 | * Enumeration of CLK_PROG source types. | ||
57 | */ | ||
58 | #define CTRL_CLK_PROG_1X_SOURCE_PLL 0x00 | ||
59 | #define CTRL_CLK_PROG_1X_SOURCE_ONE_SOURCE 0x01 | ||
60 | #define CTRL_CLK_PROG_1X_SOURCE_FLL 0x02 | ||
61 | #define CTRL_CLK_PROG_1X_SOURCE_INVALID 255 | ||
62 | |||
63 | #define CTRL_CLK_CLK_PROG_1X_MASTER_VF_ENTRY_MAX_ENTRIES 4 | ||
64 | #define CTRL_CLK_PROG_1X_MASTER_MAX_SLAVE_ENTRIES 6 | ||
65 | |||
66 | #define CTRL_CLK_CLK_VF_POINT_IDX_INVALID 255 | ||
67 | |||
68 | #define CTRL_CLK_CLK_VF_POINT_TYPE_FREQ 0x00 | ||
69 | #define CTRL_CLK_CLK_VF_POINT_TYPE_VOLT 0x01 | ||
70 | #define CTRL_CLK_CLK_VF_POINT_TYPE_UNKNOWN 255 | ||
71 | |||
72 | struct ctrl_clk_clk_prog_1x_master_source_fll { | ||
73 | u32 base_vfsmooth_volt_uv; | ||
74 | u32 max_vf_ramprate; | ||
75 | u32 max_freq_stepsize_mhz; | ||
76 | }; | ||
77 | |||
78 | union ctrl_clk_clk_prog_1x_master_source_data { | ||
79 | struct ctrl_clk_clk_prog_1x_master_source_fll fll; | ||
80 | }; | ||
81 | |||
82 | struct ctrl_clk_clk_vf_point_info_freq { | ||
83 | u16 freq_mhz; | ||
84 | }; | ||
85 | |||
86 | struct ctrl_clk_clk_vf_point_info_volt { | ||
87 | u32 sourceVoltageuV; | ||
88 | u8 vfGainVfeEquIdx; | ||
89 | u8 clkDomainIdx; | ||
90 | }; | ||
91 | |||
92 | struct ctrl_clk_clk_prog_1x_master_vf_entry { | ||
93 | u8 vfe_idx; | ||
94 | u8 gain_vfe_idx; | ||
95 | u8 vf_point_idx_first; | ||
96 | u8 vf_point_idx_last; | ||
97 | }; | ||
98 | |||
99 | struct ctrl_clk_clk_prog_1x_master_ratio_slave_entry { | ||
100 | u8 clk_dom_idx; | ||
101 | u8 ratio; | ||
102 | }; | ||
103 | |||
104 | struct ctrl_clk_clk_prog_1x_master_table_slave_entry { | ||
105 | u8 clk_dom_idx; | ||
106 | u16 freq_mhz; | ||
107 | }; | ||
108 | |||
109 | struct ctrl_clk_clk_prog_1x_source_pll { | ||
110 | u8 pll_idx; | ||
111 | u8 freq_step_size_mhz; | ||
112 | }; | ||
113 | |||
114 | struct ctrl_clk_clk_delta { | ||
115 | int freq_delta_khz; | ||
116 | int volt_deltauv[CTRL_CLK_CLK_DELTA_MAX_VOLT_RAILS]; | ||
117 | |||
118 | }; | ||
119 | |||
120 | union ctrl_clk_clk_prog_1x_source_data { | ||
121 | struct ctrl_clk_clk_prog_1x_source_pll pll; | ||
122 | }; | ||
123 | |||
124 | struct ctrl_clk_vf_pair { | ||
125 | u16 freq_mhz; | ||
126 | u32 voltage_uv; | ||
127 | }; | ||
128 | |||
129 | struct ctrl_clk_clk_domain_list_item { | ||
130 | u32 clk_domain; | ||
131 | u32 clk_freq_khz; | ||
132 | u32 clk_flags; | ||
133 | u8 current_regime_id; | ||
134 | u8 target_regime_id; | ||
135 | }; | ||
136 | |||
137 | #define CTRL_CLK_VF_PAIR_FREQ_MHZ_GET(pvfpair) \ | ||
138 | ((pvfpair)->freq_mhz) | ||
139 | |||
140 | #define CTRL_CLK_VF_PAIR_VOLTAGE_UV_GET(pvfpair) \ | ||
141 | ((pvfpair)->voltage_uv) | ||
142 | |||
143 | #define CTRL_CLK_VF_PAIR_FREQ_MHZ_SET(pvfpair, _freqmhz) \ | ||
144 | (((pvfpair)->freq_mhz) = (_freqmhz)) | ||
145 | |||
146 | #define CTRL_CLK_VF_PAIR_FREQ_MHZ_SET(pvfpair, _freqmhz) \ | ||
147 | (((pvfpair)->freq_mhz) = (_freqmhz)) | ||
148 | |||
149 | |||
150 | #define CTRL_CLK_VF_PAIR_VOLTAGE_UV_SET(pvfpair, _voltageuv) \ | ||
151 | (((pvfpair)->voltage_uv) = (_voltageuv)) | ||
152 | |||
153 | #endif | ||