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authorVaikundanathan S <vaikuns@nvidia.com>2018-04-03 05:41:58 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-05-04 09:09:47 -0400
commit65a362c01a1adc567fa176113dfeb1834777926d (patch)
tree74c85f3b2c2b0ec880bc6ecb5980caf9effde880 /drivers/gpu/nvgpu/ctrl/ctrlclk.h
parent010439ba08891ce97c53c239b5bb8c4a2f5b5f01 (diff)
gpu: nvgpu: Update clk_vin interface as per chips_a
clk_vin data structures updated as new calibration type (v20) is added. GP106 header does not have vin calibration type. Assuming V10 if calibration type is not V20. Add fuse calibration for V20 type. Bug 200399373 Change-Id: I9449de1ecb0d0873f3bc16f46660f93fab5b9eac Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com> Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1687591 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/ctrl/ctrlclk.h')
-rw-r--r--drivers/gpu/nvgpu/ctrl/ctrlclk.h24
1 files changed, 24 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/ctrl/ctrlclk.h b/drivers/gpu/nvgpu/ctrl/ctrlclk.h
index 3a383c17..3d50f413 100644
--- a/drivers/gpu/nvgpu/ctrl/ctrlclk.h
+++ b/drivers/gpu/nvgpu/ctrl/ctrlclk.h
@@ -135,6 +135,30 @@ struct ctrl_clk_clk_delta {
135 int volt_deltauv[CTRL_CLK_CLK_DELTA_MAX_VOLT_RAILS]; 135 int volt_deltauv[CTRL_CLK_CLK_DELTA_MAX_VOLT_RAILS];
136}; 136};
137 137
138struct ctrl_clk_vin_v10 {
139 u32 slope;
140 u32 intercept;
141};
142
143struct ctrl_clk_vin_v20 {
144 s8 offset;
145 s8 gain;
146};
147
148union ctrl_clk_vin_data_v20 {
149 struct ctrl_clk_vin_v10 cal_v10;
150 struct ctrl_clk_vin_v20 cal_v20;
151};
152
153struct ctrl_clk_vin_device_info_data_v10 {
154 struct ctrl_clk_vin_v10 vin_cal;
155};
156
157struct ctrl_clk_vin_device_info_data_v20 {
158 u8 cal_type;
159 union ctrl_clk_vin_data_v20 vin_cal;
160};
161
138union ctrl_clk_clk_prog_1x_source_data { 162union ctrl_clk_clk_prog_1x_source_data {
139 struct ctrl_clk_clk_prog_1x_source_pll pll; 163 struct ctrl_clk_clk_prog_1x_source_pll pll;
140}; 164};