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authorDeepak Nibade <dnibade@nvidia.com>2015-12-18 02:05:04 -0500
committerDeepak Nibade <dnibade@nvidia.com>2016-12-27 04:52:10 -0500
commitde47308b2c2ef2d24951a7e1c4ece9964417c167 (patch)
treee35cf4a956fb2580cd63f50cdf9d422b2d0763df /drivers/gpu/nvgpu/common
parent095bd5e59d896ebab12af25ac05aa4071257ecb1 (diff)
gpu: nvgpu: add CILP support for gp10b
Add CILP support for gp10b by defining below function pointers (with detailed explanation) pre_process_sm_exception() - for CILP enabled channels, get the mask of errors - if we need to broadcast the stop_trigger, suspend all SMs - otherwise suspend only current SM - clear hww_global_esr values in h/w - gr_gp10b_set_cilp_preempt_pending() - get ctx_id - using sideband method, program FECS to generate interrupt on next ctxsw - disable and preempt the channel/TSG - set cilp_preempt_pending = true - clear single step mode - resume current SM handle_fecs_error() - we get ctxsw_intr1 upon next ctxsw - clear this interrupt - get handle of channel on which we first triggered SM exception - gr_gp10b_clear_cilp_preempt_pending() - set cilp_preempt_pending = false - send events to channel and debug session fd Bug 200156699 Change-Id: Ia765db47e68fb968fada6409609af505c079df53 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/925897 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/common')
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