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| author | seshendra Gadagottu <sgadagottu@nvidia.com> | 2017-09-18 13:46:06 -0400 |
|---|---|---|
| committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-09-19 20:45:27 -0400 |
| commit | cedb24c7a09292ec8deee9ee17e1d7defeff0241 (patch) | |
| tree | e96f83c042c59a5a052a043efc09e74e607fe64e /drivers/gpu/nvgpu/common | |
| parent | e4e6a4a73469cc6f6fc38d4e643afe746976bcb2 (diff) | |
gpu: nvgpu: gv11b: correct wl reg offset
Corrected whitelist register address offset for
gr_pri_gpcs_tpcs_sm_disp_ctrl. This offset value is
changed for gv11b from gp10b. With wrong offset value,
gl tests are generating "unhandled fecs error interrupt
0x00000002 for channel xxx".
Bug 1958308
Change-Id: Iabfbb20ea1ee4ca8567d0cda940fa1e8cbff1bac
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1562615
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
Diffstat (limited to 'drivers/gpu/nvgpu/common')
0 files changed, 0 insertions, 0 deletions