diff options
author | seshendra Gadagottu <sgadagottu@nvidia.com> | 2018-01-23 13:01:45 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-02-01 18:25:44 -0500 |
commit | a7fe3a845049b62275ab660b51b6bc1300177d22 (patch) | |
tree | af59372c7cf799d0d1ed9629d922d26c4f649052 /drivers/gpu/nvgpu/common | |
parent | 9e283f9f40be0d357e90a355eae6d3b183073184 (diff) |
gpu: nvgpu: gv11b: enable devfreq
After moving devfreq enable to end of finalize power on,
intermittent issues related to gpu booting with devfreq
enabled are fixed.
Enabled devfreq for gv11b by enabling ""nvhost_podgov"
governor in platform data.
Reused scaling functions from gp10b/gk20a.
Removed emc floor on railgate for power saving.
Added max emc frequency as floor in rail-ungate for
faster gpu boot.
Bug 2049965
Bug 2039013
Bug 200377508
Change-Id: Ia1dec278b663b9f7ed859dd953a60f3eae7ef9a0
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1644702
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/common')
-rw-r--r-- | drivers/gpu/nvgpu/common/linux/platform_gp10b_tegra.c | 14 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/linux/platform_gv11b_tegra.c | 28 |
2 files changed, 35 insertions, 7 deletions
diff --git a/drivers/gpu/nvgpu/common/linux/platform_gp10b_tegra.c b/drivers/gpu/nvgpu/common/linux/platform_gp10b_tegra.c index 36052ee3..4dd5d46e 100644 --- a/drivers/gpu/nvgpu/common/linux/platform_gp10b_tegra.c +++ b/drivers/gpu/nvgpu/common/linux/platform_gp10b_tegra.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GP10B Tegra Platform Interface | 2 | * GP10B Tegra Platform Interface |
3 | * | 3 | * |
4 | * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | 6 | * This program is free software; you can redistribute it and/or modify it |
7 | * under the terms and conditions of the GNU General Public License, | 7 | * under the terms and conditions of the GNU General Public License, |
@@ -97,7 +97,7 @@ int gp10b_tegra_get_clocks(struct device *dev) | |||
97 | return 0; | 97 | return 0; |
98 | } | 98 | } |
99 | 99 | ||
100 | static void gp10b_tegra_scale_init(struct device *dev) | 100 | void gp10b_tegra_scale_init(struct device *dev) |
101 | { | 101 | { |
102 | struct gk20a_platform *platform = gk20a_get_platform(dev); | 102 | struct gk20a_platform *platform = gk20a_get_platform(dev); |
103 | struct gk20a_scale_profile *profile = platform->g->scale_profile; | 103 | struct gk20a_scale_profile *profile = platform->g->scale_profile; |
@@ -265,7 +265,7 @@ int gp10b_tegra_reset_deassert(struct device *dev) | |||
265 | return ret; | 265 | return ret; |
266 | } | 266 | } |
267 | 267 | ||
268 | static void gp10b_tegra_prescale(struct device *dev) | 268 | void gp10b_tegra_prescale(struct device *dev) |
269 | { | 269 | { |
270 | struct gk20a *g = get_gk20a(dev); | 270 | struct gk20a *g = get_gk20a(dev); |
271 | u32 avg = 0; | 271 | u32 avg = 0; |
@@ -277,7 +277,7 @@ static void gp10b_tegra_prescale(struct device *dev) | |||
277 | gk20a_dbg_fn("done"); | 277 | gk20a_dbg_fn("done"); |
278 | } | 278 | } |
279 | 279 | ||
280 | static void gp10b_tegra_postscale(struct device *pdev, | 280 | void gp10b_tegra_postscale(struct device *pdev, |
281 | unsigned long freq) | 281 | unsigned long freq) |
282 | { | 282 | { |
283 | struct gk20a_platform *platform = gk20a_get_platform(pdev); | 283 | struct gk20a_platform *platform = gk20a_get_platform(pdev); |
@@ -286,7 +286,7 @@ static void gp10b_tegra_postscale(struct device *pdev, | |||
286 | unsigned long emc_rate; | 286 | unsigned long emc_rate; |
287 | 287 | ||
288 | gk20a_dbg_fn(""); | 288 | gk20a_dbg_fn(""); |
289 | if (profile && !gp10b_tegra_is_railgated(pdev)) { | 289 | if (profile && !platform->is_railgated(pdev)) { |
290 | unsigned long emc_scale; | 290 | unsigned long emc_scale; |
291 | 291 | ||
292 | if (freq <= gp10b_freq_table[0]) | 292 | if (freq <= gp10b_freq_table[0]) |
@@ -306,7 +306,7 @@ static void gp10b_tegra_postscale(struct device *pdev, | |||
306 | gk20a_dbg_fn("done"); | 306 | gk20a_dbg_fn("done"); |
307 | } | 307 | } |
308 | 308 | ||
309 | static long gp10b_round_clk_rate(struct device *dev, unsigned long rate) | 309 | long gp10b_round_clk_rate(struct device *dev, unsigned long rate) |
310 | { | 310 | { |
311 | struct gk20a *g = get_gk20a(dev); | 311 | struct gk20a *g = get_gk20a(dev); |
312 | struct gk20a_scale_profile *profile = g->scale_profile; | 312 | struct gk20a_scale_profile *profile = g->scale_profile; |
@@ -321,7 +321,7 @@ static long gp10b_round_clk_rate(struct device *dev, unsigned long rate) | |||
321 | return freq_table[max_states - 1]; | 321 | return freq_table[max_states - 1]; |
322 | } | 322 | } |
323 | 323 | ||
324 | static int gp10b_clk_get_freqs(struct device *dev, | 324 | int gp10b_clk_get_freqs(struct device *dev, |
325 | unsigned long **freqs, int *num_freqs) | 325 | unsigned long **freqs, int *num_freqs) |
326 | { | 326 | { |
327 | struct gk20a_platform *platform = gk20a_get_platform(dev); | 327 | struct gk20a_platform *platform = gk20a_get_platform(dev); |
diff --git a/drivers/gpu/nvgpu/common/linux/platform_gv11b_tegra.c b/drivers/gpu/nvgpu/common/linux/platform_gv11b_tegra.c index 5240480e..c56bc0f3 100644 --- a/drivers/gpu/nvgpu/common/linux/platform_gv11b_tegra.c +++ b/drivers/gpu/nvgpu/common/linux/platform_gv11b_tegra.c | |||
@@ -23,6 +23,7 @@ | |||
23 | #include <linux/reset.h> | 23 | #include <linux/reset.h> |
24 | #include <linux/hashtable.h> | 24 | #include <linux/hashtable.h> |
25 | #include <linux/clk.h> | 25 | #include <linux/clk.h> |
26 | #include <linux/platform/tegra/emc_bwmgr.h> | ||
26 | 27 | ||
27 | #include <nvgpu/nvhost.h> | 28 | #include <nvgpu/nvhost.h> |
28 | 29 | ||
@@ -34,6 +35,7 @@ | |||
34 | #include "gk20a/gk20a.h" | 35 | #include "gk20a/gk20a.h" |
35 | #include "platform_gk20a.h" | 36 | #include "platform_gk20a.h" |
36 | #include "clk.h" | 37 | #include "clk.h" |
38 | #include "scale.h" | ||
37 | 39 | ||
38 | #include "gp10b/platform_gp10b.h" | 40 | #include "gp10b/platform_gp10b.h" |
39 | #include "platform_gp10b_tegra.h" | 41 | #include "platform_gp10b_tegra.h" |
@@ -135,9 +137,16 @@ static int gv11b_tegra_railgate(struct device *dev) | |||
135 | { | 137 | { |
136 | #ifdef TEGRA194_POWER_DOMAIN_GPU | 138 | #ifdef TEGRA194_POWER_DOMAIN_GPU |
137 | struct gk20a_platform *platform = gk20a_get_platform(dev); | 139 | struct gk20a_platform *platform = gk20a_get_platform(dev); |
140 | struct gk20a_scale_profile *profile = platform->g->scale_profile; | ||
138 | struct gk20a *g = get_gk20a(dev); | 141 | struct gk20a *g = get_gk20a(dev); |
139 | int i; | 142 | int i; |
140 | 143 | ||
144 | /* remove emc frequency floor */ | ||
145 | if (profile) | ||
146 | tegra_bwmgr_set_emc( | ||
147 | (struct tegra_bwmgr_client *)profile->private_data, | ||
148 | 0, TEGRA_BWMGR_SET_EMC_FLOOR); | ||
149 | |||
141 | if (tegra_bpmp_running()) { | 150 | if (tegra_bpmp_running()) { |
142 | nvgpu_log(g, gpu_dbg_info, "bpmp running"); | 151 | nvgpu_log(g, gpu_dbg_info, "bpmp running"); |
143 | if (!tegra_powergate_is_powered(TEGRA194_POWER_DOMAIN_GPU)) { | 152 | if (!tegra_powergate_is_powered(TEGRA194_POWER_DOMAIN_GPU)) { |
@@ -164,6 +173,7 @@ static int gv11b_tegra_unrailgate(struct device *dev) | |||
164 | #ifdef TEGRA194_POWER_DOMAIN_GPU | 173 | #ifdef TEGRA194_POWER_DOMAIN_GPU |
165 | struct gk20a_platform *platform = gk20a_get_platform(dev); | 174 | struct gk20a_platform *platform = gk20a_get_platform(dev); |
166 | struct gk20a *g = get_gk20a(dev); | 175 | struct gk20a *g = get_gk20a(dev); |
176 | struct gk20a_scale_profile *profile = platform->g->scale_profile; | ||
167 | int i; | 177 | int i; |
168 | 178 | ||
169 | if (tegra_bpmp_running()) { | 179 | if (tegra_bpmp_running()) { |
@@ -182,6 +192,13 @@ static int gv11b_tegra_unrailgate(struct device *dev) | |||
182 | } else { | 192 | } else { |
183 | nvgpu_log(g, gpu_dbg_info, "bpmp not running"); | 193 | nvgpu_log(g, gpu_dbg_info, "bpmp not running"); |
184 | } | 194 | } |
195 | |||
196 | /* to start with set emc frequency floor to max rate*/ | ||
197 | if (profile) | ||
198 | tegra_bwmgr_set_emc( | ||
199 | (struct tegra_bwmgr_client *)profile->private_data, | ||
200 | tegra_bwmgr_get_max_emc_rate(), | ||
201 | TEGRA_BWMGR_SET_EMC_FLOOR); | ||
185 | #endif | 202 | #endif |
186 | return ret; | 203 | return ret; |
187 | } | 204 | } |
@@ -225,6 +242,17 @@ struct gk20a_platform gv11b_tegra_platform = { | |||
225 | .busy = gk20a_tegra_busy, | 242 | .busy = gk20a_tegra_busy, |
226 | .idle = gk20a_tegra_idle, | 243 | .idle = gk20a_tegra_idle, |
227 | 244 | ||
245 | .clk_round_rate = gp10b_round_clk_rate, | ||
246 | .get_clk_freqs = gp10b_clk_get_freqs, | ||
247 | |||
248 | /* frequency scaling configuration */ | ||
249 | .initscale = gp10b_tegra_scale_init, | ||
250 | .prescale = gp10b_tegra_prescale, | ||
251 | .postscale = gp10b_tegra_postscale, | ||
252 | .devfreq_governor = "nvhost_podgov", | ||
253 | |||
254 | .qos_notify = gk20a_scale_qos_notify, | ||
255 | |||
228 | .dump_platform_dependencies = gk20a_tegra_debug_dump, | 256 | .dump_platform_dependencies = gk20a_tegra_debug_dump, |
229 | 257 | ||
230 | .soc_name = "tegra19x", | 258 | .soc_name = "tegra19x", |