gpu: nvgpu: decouple sema and hw sema

struct nvgpu_semaphore represents (mainly) a threshold value that a sema
at some index will get and struct nvgpu_semaphore_int (aka "hw_sema")
represents the allocation (and write access) of a semaphore index and
the next value that the sema at that index can have. The threshold
object doesn't need a pointer to the sema allocation that is not even
guaranteed to exist for the whole threshold lifetime, so replace the
pointer by the position of the sema in the sema pool.

This requires some modifications to pass a hw sema around explicitly
because it now represents write access more explicitly.

Delete also the index field of semaphore_int because it can be directly
derived from the offset in the sema location and is thus unnecessary.

Jira NVGPU-512

Change-Id: I40be523fd68327e2f9928f10de4f771fe24d49ee
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1658102
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 13 insertions, 11 deletions

diff --git a/drivers/gpu/nvgpu/common/semaphore.c b/drivers/gpu/nvgpu/common/semaphore.c
index dfed3588..b2238bb7 100644
--- a/drivers/gpu/nvgpu/common/semaphore.c
+++ b/drivers/gpu/nvgpu/common/semaphore.c
@@ -376,10 +376,10 @@ static int __nvgpu_init_hw_sema(struct channel_gk20a *ch)
 
         ch->hw_sema = hw_sema;
         hw_sema->ch = ch;
-        hw_sema->p = p;
-        hw_sema->idx = hw_sema_idx;
-        hw_sema->offset = SEMAPHORE_SIZE * hw_sema_idx;
-        current_value = nvgpu_mem_rd(ch->g, &p->rw_mem, hw_sema->offset);
+        hw_sema->location.pool = p;
+        hw_sema->location.offset = SEMAPHORE_SIZE * hw_sema_idx;
+        current_value = nvgpu_mem_rd(ch->g, &p->rw_mem,
+                        hw_sema->location.offset);
         nvgpu_atomic_set(&hw_sema->next_value, current_value);
 
         nvgpu_mutex_release(&p->pool_lock);
@@ -399,15 +399,16 @@ fail:
 void nvgpu_semaphore_free_hw_sema(struct channel_gk20a *ch)
 {
         struct nvgpu_semaphore_pool *p = ch->vm->sema_pool;
+        struct nvgpu_semaphore_int *hw_sema = ch->hw_sema;
+        int idx = hw_sema->location.offset / SEMAPHORE_SIZE;
 
         BUG_ON(!p);
 
         nvgpu_mutex_acquire(&p->pool_lock);
 
-        clear_bit(ch->hw_sema->idx, p->semas_alloced);
+        clear_bit(idx, p->semas_alloced);
 
-        /* Make sure that when the ch is re-opened it will get a new HW sema. */
-        nvgpu_kfree(ch->g, ch->hw_sema);
+        nvgpu_kfree(ch->g, hw_sema);
         ch->hw_sema = NULL;
 
         nvgpu_mutex_release(&p->pool_lock);
@@ -435,14 +436,15 @@ struct nvgpu_semaphore *nvgpu_semaphore_alloc(struct channel_gk20a *ch)
                 return NULL;
 
         nvgpu_ref_init(&s->ref);
-        s->hw_sema = ch->hw_sema;
+        s->g = ch->g;
+        s->location = ch->hw_sema->location;
         nvgpu_atomic_set(&s->value, 0);
 
         /*
          * Take a ref on the pool so that we can keep this pool alive for
          * as long as this semaphore is alive.
          */
-        nvgpu_semaphore_pool_get(s->hw_sema->p);
+        nvgpu_semaphore_pool_get(s->location.pool);
 
         gpu_sema_dbg(ch->g, "Allocated semaphore (c=%d)", ch->chid);
 
@@ -454,9 +456,9 @@ static void nvgpu_semaphore_free(struct nvgpu_ref *ref)
         struct nvgpu_semaphore *s =
                 container_of(ref, struct nvgpu_semaphore, ref);
 
-        nvgpu_semaphore_pool_put(s->hw_sema->p);
+        nvgpu_semaphore_pool_put(s->location.pool);
 
-        nvgpu_kfree(s->hw_sema->ch->g, s);
+        nvgpu_kfree(s->g, s);
 }
 
 void nvgpu_semaphore_put(struct nvgpu_semaphore *s)