gpu: nvgpu: Falcon controller halt interrupt status clear

- Added nvgpu_flcn_clear_halt_intr_status() to
Wait for halt interrupt status clear by
clear_halt_interrupt_status() HAL within timeout

- Added gk20a_flcn_clear_halt_interrupt_status()
to clear falcon controller halt interrupt status

- Replaced flacon halt interrupt clear with
nvgpu_flcn_clear_halt_intr_status() method

NVGPU JIRA-99

Change-Id: I762a3c01cd1d02028eb6aaa9898a50be94376619
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master/r/1511333
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>

1 files changed, 28 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/common/falcon/falcon.c b/drivers/gpu/nvgpu/common/falcon/falcon.c
index ba2fb3fe..3795dd09 100644
--- a/drivers/gpu/nvgpu/common/falcon/falcon.c
+++ b/drivers/gpu/nvgpu/common/falcon/falcon.c
@@ -122,6 +122,34 @@ int nvgpu_flcn_wait_for_halt(struct nvgpu_falcon *flcn, unsigned int timeout)
         return status;
 }
 
+int nvgpu_flcn_clear_halt_intr_status(struct nvgpu_falcon *flcn,
+        unsigned int timeout)
+{
+        struct gk20a *g = flcn->g;
+        struct nvgpu_falcon_ops *flcn_ops = &flcn->flcn_ops;
+        struct nvgpu_timeout to;
+        int status = 0;
+
+        if (!flcn_ops->clear_halt_interrupt_status) {
+                nvgpu_warn(flcn->g, "Invalid op on falcon 0x%x ",
+                        flcn->flcn_id);
+                return -EINVAL;
+        }
+
+        nvgpu_timeout_init(g, &to, timeout, NVGPU_TIMER_CPU_TIMER);
+        do {
+                if (flcn_ops->clear_halt_interrupt_status(flcn))
+                        break;
+
+                nvgpu_udelay(1);
+        } while (!nvgpu_timeout_expired(&to));
+
+        if (nvgpu_timeout_peek_expired(&to))
+                status = -EBUSY;
+
+        return status;
+}
+
 bool nvgpu_flcn_get_idle_status(struct nvgpu_falcon *flcn)
 {
         struct nvgpu_falcon_ops *flcn_ops = &flcn->flcn_ops;