diff options
author | Terje Bergstrom <tbergstrom@nvidia.com> | 2018-08-10 17:09:36 -0400 |
---|---|---|
committer | Bo Yan <byan@nvidia.com> | 2018-08-20 14:00:59 -0400 |
commit | 227c6f7b7a499dd58e0db6859736cfe586ef0897 (patch) | |
tree | d354f8422647021693aefefa5124d865c29ecd32 /drivers/gpu/nvgpu/common | |
parent | 9e69e0cf978b53706f55ffb873e3966b4bb3a7a8 (diff) |
gpu: nvgpu: Move fuse HAL to common
Move implementation of fuse HAL to common/fuse. Also implements new
fuse query functions for FBIO, FBP, TPC floorsweeping and security
fuses.
JIRA NVGPU-957
Change-Id: I55e256a4f1b59d50a721d4942907f70dc57467c4
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1797177
Diffstat (limited to 'drivers/gpu/nvgpu/common')
-rw-r--r-- | drivers/gpu/nvgpu/common/fuse/fuse_gm20b.c | 126 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/fuse/fuse_gm20b.h | 44 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/fuse/fuse_gp106.c | 230 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/fuse/fuse_gp106.h | 39 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/fuse/fuse_gp10b.c | 104 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/fuse/fuse_gp10b.h | 34 |
6 files changed, 577 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/common/fuse/fuse_gm20b.c b/drivers/gpu/nvgpu/common/fuse/fuse_gm20b.c new file mode 100644 index 00000000..c790e297 --- /dev/null +++ b/drivers/gpu/nvgpu/common/fuse/fuse_gm20b.c | |||
@@ -0,0 +1,126 @@ | |||
1 | /* | ||
2 | * GM20B FUSE | ||
3 | * | ||
4 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the "Software"), | ||
8 | * to deal in the Software without restriction, including without limitation | ||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
11 | * Software is furnished to do so, subject to the following conditions: | ||
12 | * | ||
13 | * The above copyright notice and this permission notice shall be included in | ||
14 | * all copies or substantial portions of the Software. | ||
15 | * | ||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
22 | * DEALINGS IN THE SOFTWARE. | ||
23 | */ | ||
24 | |||
25 | #include <nvgpu/types.h> | ||
26 | #include <nvgpu/fuse.h> | ||
27 | #include <nvgpu/enabled.h> | ||
28 | #include <nvgpu/io.h> | ||
29 | |||
30 | #include "gk20a/gk20a.h" | ||
31 | |||
32 | #include "fuse_gm20b.h" | ||
33 | |||
34 | #include <nvgpu/hw/gm20b/hw_fuse_gm20b.h> | ||
35 | |||
36 | int gm20b_fuse_check_priv_security(struct gk20a *g) | ||
37 | { | ||
38 | u32 gcplex_config; | ||
39 | |||
40 | if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { | ||
41 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); | ||
42 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); | ||
43 | nvgpu_log(g, gpu_dbg_info, "priv sec is enabled in fmodel"); | ||
44 | return 0; | ||
45 | } | ||
46 | |||
47 | if (nvgpu_tegra_fuse_read_gcplex_config_fuse(g, &gcplex_config)) { | ||
48 | nvgpu_err(g, "err reading gcplex config fuse, check fuse clk"); | ||
49 | return -EINVAL; | ||
50 | } | ||
51 | |||
52 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); | ||
53 | |||
54 | if (gk20a_readl(g, fuse_opt_priv_sec_en_r())) { | ||
55 | /* | ||
56 | * all falcons have to boot in LS mode and this needs | ||
57 | * wpr_enabled set to 1 and vpr_auto_fetch_disable | ||
58 | * set to 0. In this case gmmu tries to pull wpr | ||
59 | * and vpr settings from tegra mc | ||
60 | */ | ||
61 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); | ||
62 | if ((gcplex_config & | ||
63 | GCPLEX_CONFIG_WPR_ENABLED_MASK) && | ||
64 | !(gcplex_config & | ||
65 | GCPLEX_CONFIG_VPR_AUTO_FETCH_DISABLE_MASK)) { | ||
66 | if (gk20a_readl(g, fuse_opt_sec_debug_en_r())) | ||
67 | nvgpu_log(g, gpu_dbg_info, | ||
68 | "gcplex_config = 0x%08x, " | ||
69 | "secure mode: ACR debug", | ||
70 | gcplex_config); | ||
71 | else | ||
72 | nvgpu_log(g, gpu_dbg_info, | ||
73 | "gcplex_config = 0x%08x, " | ||
74 | "secure mode: ACR non debug", | ||
75 | gcplex_config); | ||
76 | } else { | ||
77 | nvgpu_err(g, "gcplex_config = 0x%08x " | ||
78 | "invalid wpr_enabled/vpr_auto_fetch_disable " | ||
79 | "with priv_sec_en", gcplex_config); | ||
80 | /* do not try to boot GPU */ | ||
81 | return -EINVAL; | ||
82 | } | ||
83 | } else { | ||
84 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); | ||
85 | nvgpu_log(g, gpu_dbg_info, | ||
86 | "gcplex_config = 0x%08x, non secure mode", | ||
87 | gcplex_config); | ||
88 | } | ||
89 | |||
90 | return 0; | ||
91 | } | ||
92 | |||
93 | u32 gm20b_fuse_status_opt_fbio(struct gk20a *g) | ||
94 | { | ||
95 | return nvgpu_readl(g, fuse_status_opt_fbio_r()); | ||
96 | } | ||
97 | |||
98 | u32 gm20b_fuse_status_opt_fbp(struct gk20a *g) | ||
99 | { | ||
100 | return nvgpu_readl(g, fuse_status_opt_fbp_r()); | ||
101 | } | ||
102 | |||
103 | u32 gm20b_fuse_status_opt_rop_l2_fbp(struct gk20a *g, u32 fbp) | ||
104 | { | ||
105 | return nvgpu_readl(g, fuse_status_opt_rop_l2_fbp_r(fbp)); | ||
106 | } | ||
107 | |||
108 | u32 gm20b_fuse_status_opt_tpc_gpc(struct gk20a *g, u32 gpc) | ||
109 | { | ||
110 | return nvgpu_readl(g, fuse_status_opt_tpc_gpc_r(gpc)); | ||
111 | } | ||
112 | |||
113 | void gm20b_fuse_ctrl_opt_tpc_gpc(struct gk20a *g, u32 gpc, u32 val) | ||
114 | { | ||
115 | nvgpu_writel(g, fuse_ctrl_opt_tpc_gpc_r(gpc), val); | ||
116 | } | ||
117 | |||
118 | u32 gm20b_fuse_opt_sec_debug_en(struct gk20a *g) | ||
119 | { | ||
120 | return nvgpu_readl(g, fuse_opt_sec_debug_en_r()); | ||
121 | } | ||
122 | |||
123 | u32 gm20b_fuse_opt_priv_sec_en(struct gk20a *g) | ||
124 | { | ||
125 | return gk20a_readl(g, fuse_opt_priv_sec_en_r()); | ||
126 | } | ||
diff --git a/drivers/gpu/nvgpu/common/fuse/fuse_gm20b.h b/drivers/gpu/nvgpu/common/fuse/fuse_gm20b.h new file mode 100644 index 00000000..5e2d194b --- /dev/null +++ b/drivers/gpu/nvgpu/common/fuse/fuse_gm20b.h | |||
@@ -0,0 +1,44 @@ | |||
1 | /* | ||
2 | * GM20B FUSE | ||
3 | * | ||
4 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the "Software"), | ||
8 | * to deal in the Software without restriction, including without limitation | ||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
11 | * Software is furnished to do so, subject to the following conditions: | ||
12 | * | ||
13 | * The above copyright notice and this permission notice shall be included in | ||
14 | * all copies or substantial portions of the Software. | ||
15 | * | ||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
22 | * DEALINGS IN THE SOFTWARE. | ||
23 | */ | ||
24 | |||
25 | #ifndef _NVGPU_GM20B_FUSE | ||
26 | #define _NVGPU_GM20B_FUSE | ||
27 | |||
28 | #define GCPLEX_CONFIG_VPR_AUTO_FETCH_DISABLE_MASK ((u32)(1 << 0)) | ||
29 | #define GCPLEX_CONFIG_VPR_ENABLED_MASK ((u32)(1 << 1)) | ||
30 | #define GCPLEX_CONFIG_WPR_ENABLED_MASK ((u32)(1 << 2)) | ||
31 | |||
32 | |||
33 | struct gk20a; | ||
34 | |||
35 | int gm20b_fuse_check_priv_security(struct gk20a *g); | ||
36 | u32 gm20b_fuse_status_opt_fbio(struct gk20a *g); | ||
37 | u32 gm20b_fuse_status_opt_fbp(struct gk20a *g); | ||
38 | u32 gm20b_fuse_status_opt_rop_l2_fbp(struct gk20a *g, u32 fbp); | ||
39 | u32 gm20b_fuse_status_opt_tpc_gpc(struct gk20a *g, u32 gpc); | ||
40 | void gm20b_fuse_ctrl_opt_tpc_gpc(struct gk20a *g, u32 gpc, u32 val); | ||
41 | u32 gm20b_fuse_opt_sec_debug_en(struct gk20a *g); | ||
42 | u32 gm20b_fuse_opt_priv_sec_en(struct gk20a *g); | ||
43 | |||
44 | #endif | ||
diff --git a/drivers/gpu/nvgpu/common/fuse/fuse_gp106.c b/drivers/gpu/nvgpu/common/fuse/fuse_gp106.c new file mode 100644 index 00000000..17951e27 --- /dev/null +++ b/drivers/gpu/nvgpu/common/fuse/fuse_gp106.c | |||
@@ -0,0 +1,230 @@ | |||
1 | /* | ||
2 | * GP106 FUSE | ||
3 | * | ||
4 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the "Software"), | ||
8 | * to deal in the Software without restriction, including without limitation | ||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
11 | * Software is furnished to do so, subject to the following conditions: | ||
12 | * | ||
13 | * The above copyright notice and this permission notice shall be included in | ||
14 | * all copies or substantial portions of the Software. | ||
15 | * | ||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
22 | * DEALINGS IN THE SOFTWARE. | ||
23 | */ | ||
24 | |||
25 | #include <nvgpu/enabled.h> | ||
26 | #include <nvgpu/io.h> | ||
27 | |||
28 | #include "gk20a/gk20a.h" | ||
29 | |||
30 | #include "fuse_gp106.h" | ||
31 | |||
32 | #include <nvgpu/hw/gp106/hw_fuse_gp106.h> | ||
33 | |||
34 | int gp106_fuse_check_priv_security(struct gk20a *g) | ||
35 | { | ||
36 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); | ||
37 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true); | ||
38 | |||
39 | return 0; | ||
40 | } | ||
41 | |||
42 | u32 gp106_fuse_read_vin_cal_fuse_rev(struct gk20a *g) | ||
43 | { | ||
44 | return fuse_vin_cal_fuse_rev_data_v( | ||
45 | gk20a_readl(g, fuse_vin_cal_fuse_rev_r())); | ||
46 | } | ||
47 | |||
48 | u32 gp106_fuse_read_vin_cal_slope_intercept_fuse(struct gk20a *g, | ||
49 | u32 vin_id, u32 *slope, | ||
50 | u32 *intercept) | ||
51 | { | ||
52 | u32 data = 0; | ||
53 | u32 interceptdata = 0; | ||
54 | u32 slopedata = 0; | ||
55 | u32 gpc0data; | ||
56 | u32 gpc0slopedata; | ||
57 | u32 gpc0interceptdata; | ||
58 | |||
59 | /* read gpc0 irrespective of vin id */ | ||
60 | gpc0data = gk20a_readl(g, fuse_vin_cal_gpc0_r()); | ||
61 | if (gpc0data == 0xFFFFFFFF) | ||
62 | return -EINVAL; | ||
63 | |||
64 | switch (vin_id) { | ||
65 | case CTRL_CLK_VIN_ID_GPC0: | ||
66 | break; | ||
67 | |||
68 | case CTRL_CLK_VIN_ID_GPC1: | ||
69 | data = gk20a_readl(g, fuse_vin_cal_gpc1_delta_r()); | ||
70 | break; | ||
71 | |||
72 | case CTRL_CLK_VIN_ID_GPC2: | ||
73 | data = gk20a_readl(g, fuse_vin_cal_gpc2_delta_r()); | ||
74 | break; | ||
75 | |||
76 | case CTRL_CLK_VIN_ID_GPC3: | ||
77 | data = gk20a_readl(g, fuse_vin_cal_gpc3_delta_r()); | ||
78 | break; | ||
79 | |||
80 | case CTRL_CLK_VIN_ID_GPC4: | ||
81 | data = gk20a_readl(g, fuse_vin_cal_gpc4_delta_r()); | ||
82 | break; | ||
83 | |||
84 | case CTRL_CLK_VIN_ID_GPC5: | ||
85 | data = gk20a_readl(g, fuse_vin_cal_gpc5_delta_r()); | ||
86 | break; | ||
87 | |||
88 | case CTRL_CLK_VIN_ID_SYS: | ||
89 | case CTRL_CLK_VIN_ID_XBAR: | ||
90 | case CTRL_CLK_VIN_ID_LTC: | ||
91 | data = gk20a_readl(g, fuse_vin_cal_shared_delta_r()); | ||
92 | break; | ||
93 | |||
94 | case CTRL_CLK_VIN_ID_SRAM: | ||
95 | data = gk20a_readl(g, fuse_vin_cal_sram_delta_r()); | ||
96 | break; | ||
97 | |||
98 | default: | ||
99 | return -EINVAL; | ||
100 | } | ||
101 | if (data == 0xFFFFFFFF) | ||
102 | return -EINVAL; | ||
103 | |||
104 | gpc0interceptdata = (fuse_vin_cal_gpc0_icpt_int_data_v(gpc0data) << | ||
105 | fuse_vin_cal_gpc0_icpt_frac_data_s()) + | ||
106 | fuse_vin_cal_gpc0_icpt_frac_data_v(gpc0data); | ||
107 | gpc0interceptdata = (gpc0interceptdata * 1000U) >> | ||
108 | fuse_vin_cal_gpc0_icpt_frac_data_s(); | ||
109 | |||
110 | switch (vin_id) { | ||
111 | case CTRL_CLK_VIN_ID_GPC0: | ||
112 | break; | ||
113 | |||
114 | case CTRL_CLK_VIN_ID_GPC1: | ||
115 | case CTRL_CLK_VIN_ID_GPC2: | ||
116 | case CTRL_CLK_VIN_ID_GPC3: | ||
117 | case CTRL_CLK_VIN_ID_GPC4: | ||
118 | case CTRL_CLK_VIN_ID_GPC5: | ||
119 | case CTRL_CLK_VIN_ID_SYS: | ||
120 | case CTRL_CLK_VIN_ID_XBAR: | ||
121 | case CTRL_CLK_VIN_ID_LTC: | ||
122 | interceptdata = (fuse_vin_cal_gpc1_delta_icpt_int_data_v(data) << | ||
123 | fuse_vin_cal_gpc1_delta_icpt_frac_data_s()) + | ||
124 | fuse_vin_cal_gpc1_delta_icpt_frac_data_v(data); | ||
125 | interceptdata = (interceptdata * 1000U) >> | ||
126 | fuse_vin_cal_gpc1_delta_icpt_frac_data_s(); | ||
127 | break; | ||
128 | |||
129 | case CTRL_CLK_VIN_ID_SRAM: | ||
130 | interceptdata = (fuse_vin_cal_sram_delta_icpt_int_data_v(data) << | ||
131 | fuse_vin_cal_sram_delta_icpt_frac_data_s()) + | ||
132 | fuse_vin_cal_sram_delta_icpt_frac_data_v(data); | ||
133 | interceptdata = (interceptdata * 1000U) >> | ||
134 | fuse_vin_cal_sram_delta_icpt_frac_data_s(); | ||
135 | break; | ||
136 | |||
137 | default: | ||
138 | return -EINVAL; | ||
139 | } | ||
140 | |||
141 | if (fuse_vin_cal_gpc1_delta_icpt_sign_data_v(data)) | ||
142 | *intercept = gpc0interceptdata - interceptdata; | ||
143 | else | ||
144 | *intercept = gpc0interceptdata + interceptdata; | ||
145 | |||
146 | /* slope */ | ||
147 | gpc0slopedata = (fuse_vin_cal_gpc0_slope_int_data_v(gpc0data) << | ||
148 | fuse_vin_cal_gpc0_slope_frac_data_s()) + | ||
149 | fuse_vin_cal_gpc0_slope_frac_data_v(gpc0data); | ||
150 | gpc0slopedata = (gpc0slopedata * 1000U) >> | ||
151 | fuse_vin_cal_gpc0_slope_frac_data_s(); | ||
152 | switch (vin_id) { | ||
153 | case CTRL_CLK_VIN_ID_GPC0: | ||
154 | break; | ||
155 | |||
156 | case CTRL_CLK_VIN_ID_GPC1: | ||
157 | case CTRL_CLK_VIN_ID_GPC2: | ||
158 | case CTRL_CLK_VIN_ID_GPC3: | ||
159 | case CTRL_CLK_VIN_ID_GPC4: | ||
160 | case CTRL_CLK_VIN_ID_GPC5: | ||
161 | case CTRL_CLK_VIN_ID_SYS: | ||
162 | case CTRL_CLK_VIN_ID_XBAR: | ||
163 | case CTRL_CLK_VIN_ID_LTC: | ||
164 | case CTRL_CLK_VIN_ID_SRAM: | ||
165 | slopedata = | ||
166 | (fuse_vin_cal_gpc1_delta_slope_int_data_v(data)) * 1000; | ||
167 | break; | ||
168 | |||
169 | default: | ||
170 | return -EINVAL; | ||
171 | } | ||
172 | |||
173 | if (fuse_vin_cal_gpc1_delta_slope_sign_data_v(data)) | ||
174 | *slope = gpc0slopedata - slopedata; | ||
175 | else | ||
176 | *slope = gpc0slopedata + slopedata; | ||
177 | return 0; | ||
178 | } | ||
179 | |||
180 | u32 gp106_fuse_read_vin_cal_gain_offset_fuse(struct gk20a *g, | ||
181 | u32 vin_id, s8 *gain, | ||
182 | s8 *offset) | ||
183 | { | ||
184 | u32 data = 0; | ||
185 | |||
186 | switch (vin_id) { | ||
187 | case CTRL_CLK_VIN_ID_GPC0: | ||
188 | data = gk20a_readl(g, fuse_vin_cal_gpc0_r()); | ||
189 | break; | ||
190 | |||
191 | case CTRL_CLK_VIN_ID_GPC1: | ||
192 | data = gk20a_readl(g, fuse_vin_cal_gpc1_delta_r()); | ||
193 | break; | ||
194 | |||
195 | case CTRL_CLK_VIN_ID_GPC2: | ||
196 | data = gk20a_readl(g, fuse_vin_cal_gpc2_delta_r()); | ||
197 | break; | ||
198 | |||
199 | case CTRL_CLK_VIN_ID_GPC3: | ||
200 | data = gk20a_readl(g, fuse_vin_cal_gpc3_delta_r()); | ||
201 | break; | ||
202 | |||
203 | case CTRL_CLK_VIN_ID_GPC4: | ||
204 | data = gk20a_readl(g, fuse_vin_cal_gpc4_delta_r()); | ||
205 | break; | ||
206 | |||
207 | case CTRL_CLK_VIN_ID_GPC5: | ||
208 | data = gk20a_readl(g, fuse_vin_cal_gpc5_delta_r()); | ||
209 | break; | ||
210 | |||
211 | case CTRL_CLK_VIN_ID_SYS: | ||
212 | case CTRL_CLK_VIN_ID_XBAR: | ||
213 | case CTRL_CLK_VIN_ID_LTC: | ||
214 | data = gk20a_readl(g, fuse_vin_cal_shared_delta_r()); | ||
215 | break; | ||
216 | |||
217 | case CTRL_CLK_VIN_ID_SRAM: | ||
218 | data = gk20a_readl(g, fuse_vin_cal_sram_delta_r()); | ||
219 | break; | ||
220 | |||
221 | default: | ||
222 | return -EINVAL; | ||
223 | } | ||
224 | if (data == 0xFFFFFFFF) | ||
225 | return -EINVAL; | ||
226 | *gain = (s8) (data >> 16) & 0x1f; | ||
227 | *offset = (s8) data & 0x7f; | ||
228 | |||
229 | return 0; | ||
230 | } | ||
diff --git a/drivers/gpu/nvgpu/common/fuse/fuse_gp106.h b/drivers/gpu/nvgpu/common/fuse/fuse_gp106.h new file mode 100644 index 00000000..f014ee8c --- /dev/null +++ b/drivers/gpu/nvgpu/common/fuse/fuse_gp106.h | |||
@@ -0,0 +1,39 @@ | |||
1 | /* | ||
2 | * GP106 FUSE | ||
3 | * | ||
4 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the "Software"), | ||
8 | * to deal in the Software without restriction, including without limitation | ||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
11 | * Software is furnished to do so, subject to the following conditions: | ||
12 | * | ||
13 | * The above copyright notice and this permission notice shall be included in | ||
14 | * all copies or substantial portions of the Software. | ||
15 | * | ||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
22 | * DEALINGS IN THE SOFTWARE. | ||
23 | */ | ||
24 | |||
25 | #ifndef _NVGPU_GP106_FUSE | ||
26 | #define _NVGPU_GP106_FUSE | ||
27 | |||
28 | struct gk20a; | ||
29 | |||
30 | int gp106_fuse_check_priv_security(struct gk20a *g); | ||
31 | u32 gp106_fuse_read_vin_cal_fuse_rev(struct gk20a *g); | ||
32 | u32 gp106_fuse_read_vin_cal_slope_intercept_fuse(struct gk20a *g, | ||
33 | u32 vin_id, u32 *slope, | ||
34 | u32 *intercept); | ||
35 | u32 gp106_fuse_read_vin_cal_gain_offset_fuse(struct gk20a *g, | ||
36 | u32 vin_id, s8 *gain, | ||
37 | s8 *offset); | ||
38 | |||
39 | #endif | ||
diff --git a/drivers/gpu/nvgpu/common/fuse/fuse_gp10b.c b/drivers/gpu/nvgpu/common/fuse/fuse_gp10b.c new file mode 100644 index 00000000..3a26e1b9 --- /dev/null +++ b/drivers/gpu/nvgpu/common/fuse/fuse_gp10b.c | |||
@@ -0,0 +1,104 @@ | |||
1 | /* | ||
2 | * GP10B FUSE | ||
3 | * | ||
4 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the "Software"), | ||
8 | * to deal in the Software without restriction, including without limitation | ||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
11 | * Software is furnished to do so, subject to the following conditions: | ||
12 | * | ||
13 | * The above copyright notice and this permission notice shall be included in | ||
14 | * all copies or substantial portions of the Software. | ||
15 | * | ||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
22 | * DEALINGS IN THE SOFTWARE. | ||
23 | */ | ||
24 | |||
25 | #include <nvgpu/types.h> | ||
26 | #include <nvgpu/fuse.h> | ||
27 | #include <nvgpu/enabled.h> | ||
28 | #include <nvgpu/io.h> | ||
29 | |||
30 | #include "gk20a/gk20a.h" | ||
31 | |||
32 | #include "fuse_gm20b.h" | ||
33 | #include "fuse_gp10b.h" | ||
34 | |||
35 | #include <nvgpu/hw/gp10b/hw_fuse_gp10b.h> | ||
36 | |||
37 | int gp10b_fuse_check_priv_security(struct gk20a *g) | ||
38 | { | ||
39 | u32 gcplex_config; | ||
40 | |||
41 | if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { | ||
42 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); | ||
43 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); | ||
44 | nvgpu_log(g, gpu_dbg_info, "priv sec is disabled in fmodel"); | ||
45 | return 0; | ||
46 | } | ||
47 | |||
48 | if (nvgpu_tegra_fuse_read_gcplex_config_fuse(g, &gcplex_config)) { | ||
49 | nvgpu_err(g, "err reading gcplex config fuse, check fuse clk"); | ||
50 | return -EINVAL; | ||
51 | } | ||
52 | |||
53 | if (gk20a_readl(g, fuse_opt_priv_sec_en_r())) { | ||
54 | /* | ||
55 | * all falcons have to boot in LS mode and this needs | ||
56 | * wpr_enabled set to 1 and vpr_auto_fetch_disable | ||
57 | * set to 0. In this case gmmu tries to pull wpr | ||
58 | * and vpr settings from tegra mc | ||
59 | */ | ||
60 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); | ||
61 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true); | ||
62 | if ((gcplex_config & | ||
63 | GCPLEX_CONFIG_WPR_ENABLED_MASK) && | ||
64 | !(gcplex_config & | ||
65 | GCPLEX_CONFIG_VPR_AUTO_FETCH_DISABLE_MASK)) { | ||
66 | if (gk20a_readl(g, fuse_opt_sec_debug_en_r())) | ||
67 | nvgpu_log(g, gpu_dbg_info, | ||
68 | "gcplex_config = 0x%08x, " | ||
69 | "secure mode: ACR debug", | ||
70 | gcplex_config); | ||
71 | else | ||
72 | nvgpu_log(g, gpu_dbg_info, | ||
73 | "gcplex_config = 0x%08x, " | ||
74 | "secure mode: ACR non debug", | ||
75 | gcplex_config); | ||
76 | |||
77 | } else { | ||
78 | nvgpu_err(g, "gcplex_config = 0x%08x " | ||
79 | "invalid wpr_enabled/vpr_auto_fetch_disable " | ||
80 | "with priv_sec_en", gcplex_config); | ||
81 | /* do not try to boot GPU */ | ||
82 | return -EINVAL; | ||
83 | } | ||
84 | } else { | ||
85 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); | ||
86 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); | ||
87 | nvgpu_log(g, gpu_dbg_info, | ||
88 | "gcplex_config = 0x%08x, non secure mode", | ||
89 | gcplex_config); | ||
90 | } | ||
91 | |||
92 | return 0; | ||
93 | } | ||
94 | |||
95 | bool gp10b_fuse_is_opt_ecc_enable(struct gk20a *g) | ||
96 | { | ||
97 | return gk20a_readl(g, fuse_opt_ecc_en_r()) != 0U; | ||
98 | } | ||
99 | |||
100 | bool gp10b_fuse_is_opt_feature_override_disable(struct gk20a *g) | ||
101 | { | ||
102 | return gk20a_readl(g, | ||
103 | fuse_opt_feature_fuses_override_disable_r()) != 0U; | ||
104 | } | ||
diff --git a/drivers/gpu/nvgpu/common/fuse/fuse_gp10b.h b/drivers/gpu/nvgpu/common/fuse/fuse_gp10b.h new file mode 100644 index 00000000..d9037e22 --- /dev/null +++ b/drivers/gpu/nvgpu/common/fuse/fuse_gp10b.h | |||
@@ -0,0 +1,34 @@ | |||
1 | /* | ||
2 | * GP10B FUSE | ||
3 | * | ||
4 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the "Software"), | ||
8 | * to deal in the Software without restriction, including without limitation | ||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
11 | * Software is furnished to do so, subject to the following conditions: | ||
12 | * | ||
13 | * The above copyright notice and this permission notice shall be included in | ||
14 | * all copies or substantial portions of the Software. | ||
15 | * | ||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
22 | * DEALINGS IN THE SOFTWARE. | ||
23 | */ | ||
24 | |||
25 | #ifndef _NVGPU_GP10B_FUSE | ||
26 | #define _NVGPU_GP10B_FUSE | ||
27 | |||
28 | struct gk20a; | ||
29 | |||
30 | int gp10b_fuse_check_priv_security(struct gk20a *g); | ||
31 | bool gp10b_fuse_is_opt_ecc_enable(struct gk20a *g); | ||
32 | bool gp10b_fuse_is_opt_feature_override_disable(struct gk20a *g); | ||
33 | |||
34 | #endif | ||