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authorThomas Fleury <tfleury@nvidia.com>2017-06-07 14:31:54 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2017-06-30 11:46:25 -0400
commit125c770c2a9c84d8243d015de4b515f33d45b2d7 (patch)
treef323aa174ca91247357dae071c547bbd65f0538f /drivers/gpu/nvgpu/common
parent28093a374bef54b9b68fcb2f00ae7d0529e33a3f (diff)
gpu: nvgpu: determine memory configuration in hal
Remove mem_config_idx from platform data, and instead let HAL determine which memory configuration to use. For this purpose, HAL may use PCI device identifiers, VBIOS version and possibly RAMCFG strap register. Bug 1929155 Change-Id: I9fcd67ff407382839ff81470789043fae1c81283 Reviewed-on: http://git-master/r/1497813 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> (cherry picked from commit 3f722945213bacfc5f6707059b9baccebd92cef1) Reviewed-on: https://git-master/r/1506583 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/common')
-rw-r--r--drivers/gpu/nvgpu/common/linux/pci.c6
1 files changed, 0 insertions, 6 deletions
diff --git a/drivers/gpu/nvgpu/common/linux/pci.c b/drivers/gpu/nvgpu/common/linux/pci.c
index acb1bb9f..939854e7 100644
--- a/drivers/gpu/nvgpu/common/linux/pci.c
+++ b/drivers/gpu/nvgpu/common/linux/pci.c
@@ -96,7 +96,6 @@ static struct gk20a_platform nvgpu_pci_device[] = {
96 .ina3221_dcb_index = 0, 96 .ina3221_dcb_index = 0,
97 .ina3221_i2c_address = 0x84, 97 .ina3221_i2c_address = 0x84,
98 .ina3221_i2c_port = 0x2, 98 .ina3221_i2c_port = 0x2,
99 .mem_config_idx = GP106_MEM_CONFIG_GDDR5_PG418,
100 }, 99 },
101 { /* DEVICE=0x1c36 */ 100 { /* DEVICE=0x1c36 */
102 /* ptimer src frequency in hz */ 101 /* ptimer src frequency in hz */
@@ -132,7 +131,6 @@ static struct gk20a_platform nvgpu_pci_device[] = {
132 .ina3221_dcb_index = 0, 131 .ina3221_dcb_index = 0,
133 .ina3221_i2c_address = 0x84, 132 .ina3221_i2c_address = 0x84,
134 .ina3221_i2c_port = 0x2, 133 .ina3221_i2c_port = 0x2,
135 .mem_config_idx = GP106_MEM_CONFIG_GDDR5_PG418,
136 }, 134 },
137 { /* DEVICE=0x1c37 */ 135 { /* DEVICE=0x1c37 */
138 /* ptimer src frequency in hz */ 136 /* ptimer src frequency in hz */
@@ -168,7 +166,6 @@ static struct gk20a_platform nvgpu_pci_device[] = {
168 .ina3221_dcb_index = 0, 166 .ina3221_dcb_index = 0,
169 .ina3221_i2c_address = 0x84, 167 .ina3221_i2c_address = 0x84,
170 .ina3221_i2c_port = 0x2, 168 .ina3221_i2c_port = 0x2,
171 .mem_config_idx = GP106_MEM_CONFIG_GDDR5_PG418,
172 }, 169 },
173 { /* DEVICE=0x1c75 */ 170 { /* DEVICE=0x1c75 */
174 /* ptimer src frequency in hz */ 171 /* ptimer src frequency in hz */
@@ -204,7 +201,6 @@ static struct gk20a_platform nvgpu_pci_device[] = {
204 .ina3221_dcb_index = 1, 201 .ina3221_dcb_index = 1,
205 .ina3221_i2c_address = 0x80, 202 .ina3221_i2c_address = 0x80,
206 .ina3221_i2c_port = 0x1, 203 .ina3221_i2c_port = 0x1,
207 .mem_config_idx = GP106_MEM_CONFIG_GDDR5_PG419,
208 } 204 }
209}; 205};
210 206
@@ -403,8 +399,6 @@ static int nvgpu_pci_probe(struct pci_dev *pdev,
403 g->msi_enabled = true; 399 g->msi_enabled = true;
404#endif 400#endif
405 401
406 g->mem_config_idx = platform->mem_config_idx;
407
408 g->irq_stall = pdev->irq; 402 g->irq_stall = pdev->irq;
409 g->irq_nonstall = pdev->irq; 403 g->irq_nonstall = pdev->irq;
410 if (g->irq_stall < 0) 404 if (g->irq_stall < 0)