gpu: nvgpu: common: fix MISRA Rule 10.4

MISRA Rule 10.4 only allows the usage of arithmetic operations on
operands of the same essential type category.

Adding "U" at the end of the integer literals to have same type of
operands when an arithmetic operation is performed.

This fix violations where an arithmetic operation is performed on
signed and unsigned int types.

In balloc_get_order_list() the argument "int order" has been changed to
a u64 because all callers of this function pass a u64 argument.

JIRA NVGPU-992

Change-Id: Ie2964f9f1dfb2865a9bd6e6cdd65e7cda6c1f638
Signed-off-by: Sai Nikhil <snikhil@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1784419
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Adeel Raza <araza@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 51 insertions, 51 deletions

diff --git a/drivers/gpu/nvgpu/common/vbios/bios.c b/drivers/gpu/nvgpu/common/vbios/bios.c
index 0760a6cd..fc82c2e9 100644
--- a/drivers/gpu/nvgpu/common/vbios/bios.c
+++ b/drivers/gpu/nvgpu/common/vbios/bios.c
@@ -26,15 +26,15 @@
 
 #include "gk20a/gk20a.h"
 
-#define BIT_HEADER_ID 0xb8ff
-#define BIT_HEADER_SIGNATURE 0x00544942
-#define PCI_EXP_ROM_SIG 0xaa55
-#define PCI_EXP_ROM_SIG_NV 0x4e56
+#define BIT_HEADER_ID                           0xb8ffU
+#define BIT_HEADER_SIGNATURE                    0x00544942U
+#define PCI_EXP_ROM_SIG                         0xaa55U
+#define PCI_EXP_ROM_SIG_NV                      0x4e56U
 
-#define INIT_DONE 0x71
-#define INIT_RESUME 0x72
-#define INIT_CONDITION 0x75
-#define INIT_XMEMSEL_ZM_NV_REG_ARRAY 0x8f
+#define INIT_DONE                               0x71U
+#define INIT_RESUME                             0x72U
+#define INIT_CONDITION                          0x75U
+#define INIT_XMEMSEL_ZM_NV_REG_ARRAY            0x8fU
 
 struct condition_entry {
         u32 cond_addr;
@@ -67,18 +67,18 @@ struct bit {
         u8 header_checksum;
 } __packed;
 
-#define TOKEN_ID_BIOSDATA 0x42
-#define TOKEN_ID_NVINIT_PTRS 0x49
-#define TOKEN_ID_FALCON_DATA 0x70
-#define TOKEN_ID_PERF_PTRS 0x50
-#define TOKEN_ID_CLOCK_PTRS 0x43
-#define TOKEN_ID_VIRT_PTRS 0x56
-#define TOKEN_ID_MEMORY_PTRS 0x4D
+#define TOKEN_ID_BIOSDATA                       0x42U
+#define TOKEN_ID_NVINIT_PTRS                    0x49U
+#define TOKEN_ID_FALCON_DATA                    0x70U
+#define TOKEN_ID_PERF_PTRS                      0x50U
+#define TOKEN_ID_CLOCK_PTRS                     0x43U
+#define TOKEN_ID_VIRT_PTRS                      0x56U
+#define TOKEN_ID_MEMORY_PTRS                    0x4DU
 
-#define NVLINK_CONFIG_DATA_HDR_VER_10 0x1
-#define NVLINK_CONFIG_DATA_HDR_10_SIZE 16
-#define NVLINK_CONFIG_DATA_HDR_11_SIZE 17
-#define NVLINK_CONFIG_DATA_HDR_12_SIZE 21
+#define NVLINK_CONFIG_DATA_HDR_VER_10           0x1U
+#define NVLINK_CONFIG_DATA_HDR_10_SIZE          16U
+#define NVLINK_CONFIG_DATA_HDR_11_SIZE          17U
+#define NVLINK_CONFIG_DATA_HDR_12_SIZE          21U
 
 struct nvlink_config_data_hdr_v1 {
         u8 version;
@@ -91,8 +91,8 @@ struct nvlink_config_data_hdr_v1 {
         u32 ac_coupling_mask;
 } __packed;
 
-#define MEMORY_PTRS_V1 1
-#define MEMORY_PTRS_V2 2
+#define MEMORY_PTRS_V1                          1U
+#define MEMORY_PTRS_V2                          2U
 
 struct memory_ptrs_v1 {
         u8 rsvd0[2];
@@ -155,11 +155,11 @@ struct falcon_ucode_table_entry_v1 {
         u32 desc_ptr;
 } __packed;
 
-#define TARGET_ID_PMU 0x01
-#define APPLICATION_ID_DEVINIT 0x04
-#define APPLICATION_ID_PRE_OS 0x01
+#define TARGET_ID_PMU                           0x01U
+#define APPLICATION_ID_DEVINIT                  0x04U
+#define APPLICATION_ID_PRE_OS                   0x01U
 
-#define FALCON_UCODE_FLAGS_VERSION_AVAILABLE 0x1
+#define FALCON_UCODE_FLAGS_VERSION_AVAILABLE    0x1U
 #define FALCON_UCODE_IS_VERSION_AVAILABLE(hdr)           \
         ((hdr.v2.v_desc & FALCON_UCODE_FLAGS_VERSION_AVAILABLE) == \
         FALCON_UCODE_FLAGS_VERSION_AVAILABLE)
@@ -170,10 +170,10 @@ struct falcon_ucode_table_entry_v1 {
  */
 
 #define FALCON_UCODE_GET_VERSION(hdr) \
-        ((hdr.v2.v_desc >> 8) & 0xff)
+        ((hdr.v2.v_desc >> 8) & 0xffU)
 
 #define FALCON_UCODE_GET_DESC_SIZE(hdr) \
-        ((hdr.v2.v_desc >> 16) & 0xffff)
+        ((hdr.v2.v_desc >> 16) & 0xffffU)
 
 struct falcon_ucode_desc_v1 {
         union {
@@ -228,7 +228,7 @@ struct application_interface_entry_v1 {
         u32 dmem_offset;
 } __packed;
 
-#define APPINFO_ID_DEVINIT 0x01
+#define APPINFO_ID_DEVINIT                      0x01U
 
 struct devinit_engine_interface {
         u16 version;
@@ -316,7 +316,7 @@ int nvgpu_bios_parse_rom(struct gk20a *g)
                                 pci_data->last_image,
                                 pci_data->max_runtime_image_len);
 
-                if (pci_data->code_type == 0x3) {
+                if (pci_data->code_type == 0x3U) {
                         pci_ext_data = (struct pci_ext_data_struct *)
                                 &g->bios.data[(offset +
                                                pci_rom->pci_data_struct_ptr +
@@ -332,9 +332,9 @@ int nvgpu_bios_parse_rom(struct gk20a *g)
                                         pci_ext_data->flags);
 
                         nvgpu_log_fn(g, "expansion rom offset %x",
-                                        pci_data->image_len * 512);
+                                        pci_data->image_len * 512U);
                         g->bios.expansion_rom_offset =
-                                pci_data->image_len * 512;
+                                (u32)pci_data->image_len * 512U;
                         offset += pci_ext_data->sub_image_len * 512;
                         last = pci_ext_data->priv_last_image;
                 } else {
@@ -344,9 +344,9 @@ int nvgpu_bios_parse_rom(struct gk20a *g)
         }
 
         nvgpu_log_info(g, "read bios");
-        for (i = 0; i < g->bios.size - 6; i++) {
+        for (i = 0; i < g->bios.size - 6U; i++) {
                 if (nvgpu_bios_rdu16(g, i) == BIT_HEADER_ID &&
-                    nvgpu_bios_rdu32(g, i+2) ==  BIT_HEADER_SIGNATURE) {
+                    nvgpu_bios_rdu32(g, i+2U) ==  BIT_HEADER_SIGNATURE) {
                         nvgpu_bios_parse_bit(g, i);
                         found = true;
                 }
@@ -394,7 +394,7 @@ u32 nvgpu_bios_get_nvlink_config_data(struct gk20a *g)
 {
         struct nvlink_config_data_hdr_v1 config;
 
-        if (g->bios.nvlink_config_data_offset == 0) {
+        if (g->bios.nvlink_config_data_offset == 0U) {
                 return -EINVAL;
         }
 
@@ -460,7 +460,7 @@ static void nvgpu_bios_parse_devinit_appinfo(struct gk20a *g, int dmem_offset)
                         interface.script_phys_base,
                         interface.script_size);
 
-        if (interface.version != 1) {
+        if (interface.version != 1U) {
                 return;
         }
         g->bios.devinit_tables_phys_base = interface.tables_phys_base;
@@ -478,7 +478,7 @@ static int nvgpu_bios_parse_appinfo_table(struct gk20a *g, int offset)
                         hdr.version, hdr.header_size,
                         hdr.entry_size, hdr.entry_count);
 
-        if (hdr.version != 1) {
+        if (hdr.version != 1U) {
                 return 0;
         }
 
@@ -588,7 +588,7 @@ static int nvgpu_bios_parse_falcon_ucode_table(struct gk20a *g, int offset)
                         hdr.entry_size, hdr.entry_count,
                         hdr.desc_version, hdr.desc_size);
 
-        if (hdr.version != 1) {
+        if (hdr.version != 1U) {
                 return -EINVAL;
         }
 
@@ -697,9 +697,9 @@ void *nvgpu_bios_get_perf_table_ptrs(struct gk20a *g,
                                         (table_id * data_size)),
                                         perf_table_id_offset);
 
-                if (perf_table_id_offset != 0) {
+                if (perf_table_id_offset != 0U) {
                         /* check is perf_table_id_offset is > 64k */
-                        if (perf_table_id_offset & ~0xFFFF) {
+                        if (perf_table_id_offset & ~0xFFFFU) {
                                 perf_table_ptr =
                                         &g->bios.data[g->bios.expansion_rom_offset +
                                                 perf_table_id_offset];
@@ -747,7 +747,7 @@ static void nvgpu_bios_parse_bit(struct gk20a *g, int offset)
                         nvgpu_bios_parse_nvinit_ptrs(g, bit_token.data_ptr);
                         break;
                 case TOKEN_ID_FALCON_DATA:
-                        if (bit_token.data_version == 2) {
+                        if (bit_token.data_version == 2U) {
                                 nvgpu_bios_parse_falcon_data_v2(g,
                                                 bit_token.data_ptr);
                         }
@@ -790,7 +790,7 @@ s8 nvgpu_bios_read_s8(struct gk20a *g, u32 offset)
 {
         u32 val;
         val = __nvgpu_bios_readbyte(g, offset);
-        val = val & 0x80 ? (val | ~0xff) : val;
+        val = val & 0x80U ? (val | ~0xffU) : val;
 
         return (s8) val;
 }
@@ -800,7 +800,7 @@ u16 nvgpu_bios_read_u16(struct gk20a *g, u32 offset)
         u16 val;
 
         val = __nvgpu_bios_readbyte(g, offset) |
-                (__nvgpu_bios_readbyte(g, offset+1) << 8);
+                (__nvgpu_bios_readbyte(g, offset+1U) << 8U);
 
         return val;
 }
@@ -810,9 +810,9 @@ u32 nvgpu_bios_read_u32(struct gk20a *g, u32 offset)
         u32 val;
 
         val = __nvgpu_bios_readbyte(g, offset) |
-                (__nvgpu_bios_readbyte(g, offset+1) << 8) |
-                (__nvgpu_bios_readbyte(g, offset+2) << 16) |
-                (__nvgpu_bios_readbyte(g, offset+3) << 24);
+                (__nvgpu_bios_readbyte(g, offset+1U) << 8U) |
+                (__nvgpu_bios_readbyte(g, offset+2U) << 16U) |
+                (__nvgpu_bios_readbyte(g, offset+3U) << 24U);
 
         return val;
 }
@@ -825,7 +825,7 @@ static void nvgpu_bios_init_xmemsel_zm_nv_reg_array(struct gk20a *g, bool *condi
 
         if (*condition) {
 
-                strap = gk20a_readl(g, gc6_sci_strap_r()) & 0xf;
+                strap = gk20a_readl(g, gc6_sci_strap_r()) & 0xfU;
 
                 index = g->bios.mem_strap_xlat_tbl_ptr ?
                         nvgpu_bios_read_u8(g, g->bios.mem_strap_xlat_tbl_ptr +
@@ -849,9 +849,9 @@ static void gp106_init_condition(struct gk20a *g, bool *condition,
         entry.cond_addr = nvgpu_bios_read_u32(g, g->bios.condition_table_ptr +
                 sizeof(entry)*condition_id);
         entry.cond_mask = nvgpu_bios_read_u32(g, g->bios.condition_table_ptr +
-                sizeof(entry)*condition_id + 4);
+                sizeof(entry)*condition_id + 4U);
         entry.cond_compare = nvgpu_bios_read_u32(g, g->bios.condition_table_ptr +
-                sizeof(entry)*condition_id + 8);
+                sizeof(entry)*condition_id + 8U);
 
         if ((gk20a_readl(g, entry.cond_addr) & entry.cond_mask)
                 != entry.cond_compare) {
@@ -879,9 +879,9 @@ int nvgpu_bios_execute_script(struct gk20a *g, u32 offset)
 
                 case INIT_XMEMSEL_ZM_NV_REG_ARRAY:
                         operand[0] = nvgpu_bios_read_u32(g, ip);
-                        operand[1] = nvgpu_bios_read_u8(g, ip+4);
-                        operand[2] = nvgpu_bios_read_u8(g, ip+5);
-                        ip += 6;
+                        operand[1] = nvgpu_bios_read_u8(g, ip+4U);
+                        operand[2] = nvgpu_bios_read_u8(g, ip+5U);
+                        ip += 6U;
 
                         nvgpu_bios_init_xmemsel_zm_nv_reg_array(g, &condition,
                                 operand[0], operand[1], operand[2], ip);