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authorTerje Bergstrom <tbergstrom@nvidia.com>2018-08-09 12:20:33 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-08-14 18:33:20 -0400
commit91390d857f6302f9c2923ec4188ea7e24ee537a2 (patch)
treee0884e79ea748d2c0bd384c29f805125a7b88fec /drivers/gpu/nvgpu/common/therm
parent02f9c99e4b4a452ded20978c5ee1e27b775b9224 (diff)
gpu: nvgpu: Move therm HAL to common
Move implementation of therm HAL to common/therm. ELCG and BLCG code was embedded in gr HAL, so moved that code to therm. Bump gk20a code to gm20b. JIRA NVGPU-955 Change-Id: I9b03e52f2832d3a1d89071a577e8ce106aaf603b Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1795989 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/common/therm')
-rw-r--r--drivers/gpu/nvgpu/common/therm/therm.c46
-rw-r--r--drivers/gpu/nvgpu/common/therm/therm_gm20b.c187
-rw-r--r--drivers/gpu/nvgpu/common/therm/therm_gm20b.h33
-rw-r--r--drivers/gpu/nvgpu/common/therm/therm_gp106.c144
-rw-r--r--drivers/gpu/nvgpu/common/therm/therm_gp106.h40
-rw-r--r--drivers/gpu/nvgpu/common/therm/therm_gp10b.c137
-rw-r--r--drivers/gpu/nvgpu/common/therm/therm_gp10b.h29
-rw-r--r--drivers/gpu/nvgpu/common/therm/therm_gv11b.c183
-rw-r--r--drivers/gpu/nvgpu/common/therm/therm_gv11b.h30
9 files changed, 829 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/common/therm/therm.c b/drivers/gpu/nvgpu/common/therm/therm.c
new file mode 100644
index 00000000..cfe8a2c1
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/therm/therm.c
@@ -0,0 +1,46 @@
1/*
2 * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#include <nvgpu/types.h>
24#include <nvgpu/log.h>
25#include <nvgpu/therm.h>
26
27#include "gk20a/gk20a.h"
28
29int nvgpu_init_therm_support(struct gk20a *g)
30{
31 u32 err = 0U;
32
33 nvgpu_log_fn(g, " ");
34
35 if (g->ops.therm.init_therm_setup_hw)
36 err = g->ops.therm.init_therm_setup_hw(g);
37 if (err)
38 return err;
39
40#ifdef CONFIG_DEBUG_FS
41 if (g->ops.therm.therm_debugfs_init)
42 g->ops.therm.therm_debugfs_init(g);
43#endif
44
45 return err;
46}
diff --git a/drivers/gpu/nvgpu/common/therm/therm_gm20b.c b/drivers/gpu/nvgpu/common/therm/therm_gm20b.c
new file mode 100644
index 00000000..023ec36a
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/therm/therm_gm20b.c
@@ -0,0 +1,187 @@
1/*
2 * GM20B THERMAL
3 *
4 * Copyright (c) 2015-2018, NVIDIA CORPORATION. All rights reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24
25#include <nvgpu/io.h>
26#include "gk20a/gk20a.h"
27
28#include "therm_gm20b.h"
29
30#include <nvgpu/hw/gm20b/hw_therm_gm20b.h>
31
32int gm20b_init_therm_setup_hw(struct gk20a *g)
33{
34 u32 v;
35
36 nvgpu_log_fn(g, " ");
37
38 /* program NV_THERM registers */
39 gk20a_writel(g, therm_use_a_r(), therm_use_a_ext_therm_0_enable_f() |
40 therm_use_a_ext_therm_1_enable_f() |
41 therm_use_a_ext_therm_2_enable_f());
42 gk20a_writel(g, therm_evt_ext_therm_0_r(),
43 therm_evt_ext_therm_0_slow_factor_f(0x2));
44 gk20a_writel(g, therm_evt_ext_therm_1_r(),
45 therm_evt_ext_therm_1_slow_factor_f(0x6));
46 gk20a_writel(g, therm_evt_ext_therm_2_r(),
47 therm_evt_ext_therm_2_slow_factor_f(0xe));
48
49 gk20a_writel(g, therm_grad_stepping_table_r(0),
50 therm_grad_stepping_table_slowdown_factor0_f(therm_grad_stepping_table_slowdown_factor0_fpdiv_by1p5_f()) |
51 therm_grad_stepping_table_slowdown_factor1_f(therm_grad_stepping_table_slowdown_factor0_fpdiv_by2_f()) |
52 therm_grad_stepping_table_slowdown_factor2_f(therm_grad_stepping_table_slowdown_factor0_fpdiv_by4_f()) |
53 therm_grad_stepping_table_slowdown_factor3_f(therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()) |
54 therm_grad_stepping_table_slowdown_factor4_f(therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()));
55 gk20a_writel(g, therm_grad_stepping_table_r(1),
56 therm_grad_stepping_table_slowdown_factor0_f(therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()) |
57 therm_grad_stepping_table_slowdown_factor1_f(therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()) |
58 therm_grad_stepping_table_slowdown_factor2_f(therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()) |
59 therm_grad_stepping_table_slowdown_factor3_f(therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()) |
60 therm_grad_stepping_table_slowdown_factor4_f(therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()));
61
62 v = gk20a_readl(g, therm_clk_timing_r(0));
63 v |= therm_clk_timing_grad_slowdown_enabled_f();
64 gk20a_writel(g, therm_clk_timing_r(0), v);
65
66 v = gk20a_readl(g, therm_config2_r());
67 v |= therm_config2_grad_enable_f(1);
68 v |= therm_config2_slowdown_factor_extended_f(1);
69 gk20a_writel(g, therm_config2_r(), v);
70
71 gk20a_writel(g, therm_grad_stepping1_r(),
72 therm_grad_stepping1_pdiv_duration_f(32));
73
74 v = gk20a_readl(g, therm_grad_stepping0_r());
75 v |= therm_grad_stepping0_feature_enable_f();
76 gk20a_writel(g, therm_grad_stepping0_r(), v);
77
78 return 0;
79}
80
81int gm20b_elcg_init_idle_filters(struct gk20a *g)
82{
83 u32 gate_ctrl, idle_filter;
84 u32 engine_id;
85 u32 active_engine_id = 0;
86 struct fifo_gk20a *f = &g->fifo;
87
88 nvgpu_log_fn(g, " ");
89
90 for (engine_id = 0; engine_id < f->num_engines; engine_id++) {
91 active_engine_id = f->active_engines_list[engine_id];
92 gate_ctrl = gk20a_readl(g, therm_gate_ctrl_r(active_engine_id));
93
94 if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
95 gate_ctrl = set_field(gate_ctrl,
96 therm_gate_ctrl_eng_delay_after_m(),
97 therm_gate_ctrl_eng_delay_after_f(4));
98 }
99
100 /* 2 * (1 << 9) = 1024 clks */
101 gate_ctrl = set_field(gate_ctrl,
102 therm_gate_ctrl_eng_idle_filt_exp_m(),
103 therm_gate_ctrl_eng_idle_filt_exp_f(9));
104 gate_ctrl = set_field(gate_ctrl,
105 therm_gate_ctrl_eng_idle_filt_mant_m(),
106 therm_gate_ctrl_eng_idle_filt_mant_f(2));
107 gk20a_writel(g, therm_gate_ctrl_r(active_engine_id), gate_ctrl);
108 }
109
110 /* default fecs_idle_filter to 0 */
111 idle_filter = gk20a_readl(g, therm_fecs_idle_filter_r());
112 idle_filter &= ~therm_fecs_idle_filter_value_m();
113 gk20a_writel(g, therm_fecs_idle_filter_r(), idle_filter);
114 /* default hubmmu_idle_filter to 0 */
115 idle_filter = gk20a_readl(g, therm_hubmmu_idle_filter_r());
116 idle_filter &= ~therm_hubmmu_idle_filter_value_m();
117 gk20a_writel(g, therm_hubmmu_idle_filter_r(), idle_filter);
118
119 nvgpu_log_fn(g, "done");
120 return 0;
121}
122
123void gm20b_therm_init_blcg_mode(struct gk20a *g, u32 mode, u32 engine)
124{
125 u32 gate_ctrl;
126
127 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG))
128 return;
129
130 gate_ctrl = gk20a_readl(g, therm_gate_ctrl_r(engine));
131
132 switch (mode) {
133 case BLCG_RUN:
134 gate_ctrl = set_field(gate_ctrl,
135 therm_gate_ctrl_blk_clk_m(),
136 therm_gate_ctrl_blk_clk_run_f());
137 break;
138 case BLCG_AUTO:
139 gate_ctrl = set_field(gate_ctrl,
140 therm_gate_ctrl_blk_clk_m(),
141 therm_gate_ctrl_blk_clk_auto_f());
142 break;
143 default:
144 nvgpu_err(g,
145 "invalid blcg mode %d", mode);
146 return;
147 }
148
149 gk20a_writel(g, therm_gate_ctrl_r(engine), gate_ctrl);
150}
151
152void gm20b_therm_init_elcg_mode(struct gk20a *g, u32 mode, u32 engine)
153{
154 u32 gate_ctrl;
155
156 gate_ctrl = gk20a_readl(g, therm_gate_ctrl_r(engine));
157
158 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_ELCG))
159 return;
160
161 switch (mode) {
162 case ELCG_RUN:
163 gate_ctrl = set_field(gate_ctrl,
164 therm_gate_ctrl_eng_clk_m(),
165 therm_gate_ctrl_eng_clk_run_f());
166 gate_ctrl = set_field(gate_ctrl,
167 therm_gate_ctrl_eng_pwr_m(),
168 /* set elpg to auto to meet hw expectation */
169 therm_gate_ctrl_eng_pwr_auto_f());
170 break;
171 case ELCG_STOP:
172 gate_ctrl = set_field(gate_ctrl,
173 therm_gate_ctrl_eng_clk_m(),
174 therm_gate_ctrl_eng_clk_stop_f());
175 break;
176 case ELCG_AUTO:
177 gate_ctrl = set_field(gate_ctrl,
178 therm_gate_ctrl_eng_clk_m(),
179 therm_gate_ctrl_eng_clk_auto_f());
180 break;
181 default:
182 nvgpu_err(g,
183 "invalid elcg mode %d", mode);
184 }
185
186 gk20a_writel(g, therm_gate_ctrl_r(engine), gate_ctrl);
187}
diff --git a/drivers/gpu/nvgpu/common/therm/therm_gm20b.h b/drivers/gpu/nvgpu/common/therm/therm_gm20b.h
new file mode 100644
index 00000000..b6dfc5b6
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/therm/therm_gm20b.h
@@ -0,0 +1,33 @@
1/*
2 * GM20B THERMAL
3 *
4 * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24#ifndef THERM_GM20B_H
25#define THERM_GM20B_H
26
27struct gk20a;
28int gm20b_init_therm_setup_hw(struct gk20a *g);
29int gm20b_elcg_init_idle_filters(struct gk20a *g);
30void gm20b_therm_init_elcg_mode(struct gk20a *g, u32 mode, u32 engine);
31void gm20b_therm_init_blcg_mode(struct gk20a *g, u32 mode, u32 engine);
32
33#endif /* THERM_GM20B_H */
diff --git a/drivers/gpu/nvgpu/common/therm/therm_gp106.c b/drivers/gpu/nvgpu/common/therm/therm_gp106.c
new file mode 100644
index 00000000..1f82aa7a
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/therm/therm_gp106.c
@@ -0,0 +1,144 @@
1/*
2 * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#include <nvgpu/io.h>
24#include "gk20a/gk20a.h"
25
26#include "therm_gp106.h"
27#include "therm/thrmpmu.h"
28
29#ifdef CONFIG_DEBUG_FS
30#include <linux/debugfs.h>
31#include "os/linux/os_linux.h"
32#endif
33
34#include <nvgpu/hw/gp106/hw_therm_gp106.h>
35
36#include <nvgpu/utils.h>
37
38void gp106_get_internal_sensor_limits(s32 *max_24_8, s32 *min_24_8)
39{
40 *max_24_8 = (0x87 << 8);
41 *min_24_8 = (((u32)-216) << 8);
42}
43
44int gp106_get_internal_sensor_curr_temp(struct gk20a *g, u32 *temp_f24_8)
45{
46 int err = 0;
47 u32 readval;
48
49 readval = gk20a_readl(g, therm_temp_sensor_tsense_r());
50
51 if (!(therm_temp_sensor_tsense_state_v(readval) &
52 therm_temp_sensor_tsense_state_valid_v())) {
53 nvgpu_err(g,
54 "Attempt to read temperature while sensor is OFF!");
55 err = -EINVAL;
56 } else if (therm_temp_sensor_tsense_state_v(readval) &
57 therm_temp_sensor_tsense_state_shadow_v()) {
58 nvgpu_err(g, "Reading temperature from SHADOWed sensor!");
59 }
60
61 // Convert from F9.5 -> F27.5 -> F24.8.
62 readval &= therm_temp_sensor_tsense_fixed_point_m();
63
64 *temp_f24_8 = readval;
65
66 return err;
67}
68
69#ifdef CONFIG_DEBUG_FS
70static int therm_get_internal_sensor_curr_temp(void *data, u64 *val)
71{
72 struct gk20a *g = (struct gk20a *)data;
73 u32 readval;
74 int err;
75
76 err = gp106_get_internal_sensor_curr_temp(g, &readval);
77 if (!err)
78 *val = readval;
79
80 return err;
81}
82DEFINE_SIMPLE_ATTRIBUTE(therm_ctrl_fops, therm_get_internal_sensor_curr_temp, NULL, "%llu\n");
83
84void gp106_therm_debugfs_init(struct gk20a *g)
85{
86 struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
87 struct dentry *dbgentry;
88
89 dbgentry = debugfs_create_file(
90 "temp", S_IRUGO, l->debugfs, g, &therm_ctrl_fops);
91 if (!dbgentry)
92 nvgpu_err(g, "debugfs entry create failed for therm_curr_temp");
93}
94#endif
95
96int gp106_elcg_init_idle_filters(struct gk20a *g)
97{
98 u32 gate_ctrl, idle_filter;
99 u32 engine_id;
100 u32 active_engine_id = 0;
101 struct fifo_gk20a *f = &g->fifo;
102
103 nvgpu_log_fn(g, " ");
104
105 for (engine_id = 0; engine_id < f->num_engines; engine_id++) {
106 active_engine_id = f->active_engines_list[engine_id];
107 gate_ctrl = gk20a_readl(g, therm_gate_ctrl_r(active_engine_id));
108
109 gate_ctrl = set_field(gate_ctrl,
110 therm_gate_ctrl_eng_idle_filt_exp_m(),
111 therm_gate_ctrl_eng_idle_filt_exp_f(2));
112 gate_ctrl = set_field(gate_ctrl,
113 therm_gate_ctrl_eng_idle_filt_mant_m(),
114 therm_gate_ctrl_eng_idle_filt_mant_f(1));
115 gate_ctrl = set_field(gate_ctrl,
116 therm_gate_ctrl_eng_delay_before_m(),
117 therm_gate_ctrl_eng_delay_before_f(0));
118 gk20a_writel(g, therm_gate_ctrl_r(active_engine_id), gate_ctrl);
119 }
120
121 /* default fecs_idle_filter to 0 */
122 idle_filter = gk20a_readl(g, therm_fecs_idle_filter_r());
123 idle_filter &= ~therm_fecs_idle_filter_value_m();
124 gk20a_writel(g, therm_fecs_idle_filter_r(), idle_filter);
125 /* default hubmmu_idle_filter to 0 */
126 idle_filter = gk20a_readl(g, therm_hubmmu_idle_filter_r());
127 idle_filter &= ~therm_hubmmu_idle_filter_value_m();
128 gk20a_writel(g, therm_hubmmu_idle_filter_r(), idle_filter);
129
130 nvgpu_log_fn(g, "done");
131 return 0;
132}
133
134u32 gp106_configure_therm_alert(struct gk20a *g, s32 curr_warn_temp)
135{
136 u32 err = 0;
137
138 if (g->curr_warn_temp != curr_warn_temp) {
139 g->curr_warn_temp = curr_warn_temp;
140 err = therm_configure_therm_alert(g);
141 }
142
143 return err;
144}
diff --git a/drivers/gpu/nvgpu/common/therm/therm_gp106.h b/drivers/gpu/nvgpu/common/therm/therm_gp106.h
new file mode 100644
index 00000000..a92c2e0f
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/therm/therm_gp106.h
@@ -0,0 +1,40 @@
1/*
2 * general thermal control structures & definitions
3 *
4 * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24
25#ifndef NVGPU_THERM_GP106_H
26#define NVGPU_THERM_GP106_H
27
28#include <nvgpu/types.h>
29
30struct gk20a;
31
32void gp106_get_internal_sensor_limits(s32 *max_24_8, s32 *min_24_8);
33int gp106_get_internal_sensor_curr_temp(struct gk20a *g, u32 *temp_f24_8);
34#ifdef CONFIG_DEBUG_FS
35void gp106_therm_debugfs_init(struct gk20a *g);
36#endif
37int gp106_elcg_init_idle_filters(struct gk20a *g);
38u32 gp106_configure_therm_alert(struct gk20a *g, s32 curr_warn_temp);
39
40#endif
diff --git a/drivers/gpu/nvgpu/common/therm/therm_gp10b.c b/drivers/gpu/nvgpu/common/therm/therm_gp10b.c
new file mode 100644
index 00000000..905ff178
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/therm/therm_gp10b.c
@@ -0,0 +1,137 @@
1/*
2 * GP10B Therm
3 *
4 * Copyright (c) 2015-2018, NVIDIA CORPORATION. All rights reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24
25#include "gk20a/gk20a.h"
26#include "therm_gp10b.h"
27
28#include <nvgpu/soc.h>
29#include <nvgpu/io.h>
30#include <nvgpu/utils.h>
31
32#include <nvgpu/hw/gp10b/hw_therm_gp10b.h>
33
34int gp10b_init_therm_setup_hw(struct gk20a *g)
35{
36 u32 v;
37
38 nvgpu_log_fn(g, " ");
39
40 /* program NV_THERM registers */
41 gk20a_writel(g, therm_use_a_r(), therm_use_a_ext_therm_0_enable_f() |
42 therm_use_a_ext_therm_1_enable_f() |
43 therm_use_a_ext_therm_2_enable_f());
44 gk20a_writel(g, therm_evt_ext_therm_0_r(),
45 therm_evt_ext_therm_0_slow_factor_f(0x2));
46 gk20a_writel(g, therm_evt_ext_therm_1_r(),
47 therm_evt_ext_therm_1_slow_factor_f(0x6));
48 gk20a_writel(g, therm_evt_ext_therm_2_r(),
49 therm_evt_ext_therm_2_slow_factor_f(0xe));
50
51 gk20a_writel(g, therm_grad_stepping_table_r(0),
52 therm_grad_stepping_table_slowdown_factor0_f(
53 therm_grad_stepping_table_slowdown_factor0_fpdiv_by1p5_f()) |
54 therm_grad_stepping_table_slowdown_factor1_f(
55 therm_grad_stepping_table_slowdown_factor0_fpdiv_by2_f()) |
56 therm_grad_stepping_table_slowdown_factor2_f(
57 therm_grad_stepping_table_slowdown_factor0_fpdiv_by4_f()) |
58 therm_grad_stepping_table_slowdown_factor3_f(
59 therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()) |
60 therm_grad_stepping_table_slowdown_factor4_f(
61 therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()));
62
63 gk20a_writel(g, therm_grad_stepping_table_r(1),
64 therm_grad_stepping_table_slowdown_factor0_f(
65 therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()) |
66 therm_grad_stepping_table_slowdown_factor1_f(
67 therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()) |
68 therm_grad_stepping_table_slowdown_factor2_f(
69 therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()) |
70 therm_grad_stepping_table_slowdown_factor3_f(
71 therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()) |
72 therm_grad_stepping_table_slowdown_factor4_f(
73 therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()));
74
75 v = gk20a_readl(g, therm_clk_timing_r(0));
76 v |= therm_clk_timing_grad_slowdown_enabled_f();
77 gk20a_writel(g, therm_clk_timing_r(0), v);
78
79 v = gk20a_readl(g, therm_config2_r());
80 v |= therm_config2_grad_enable_f(1);
81 v |= therm_config2_slowdown_factor_extended_f(1);
82 gk20a_writel(g, therm_config2_r(), v);
83
84 gk20a_writel(g, therm_grad_stepping1_r(),
85 therm_grad_stepping1_pdiv_duration_f(32));
86
87 v = gk20a_readl(g, therm_grad_stepping0_r());
88 v |= therm_grad_stepping0_feature_enable_f();
89 gk20a_writel(g, therm_grad_stepping0_r(), v);
90
91 return 0;
92}
93
94int gp10b_elcg_init_idle_filters(struct gk20a *g)
95{
96 u32 gate_ctrl, idle_filter;
97 u32 engine_id;
98 u32 active_engine_id = 0;
99 struct fifo_gk20a *f = &g->fifo;
100
101 nvgpu_log_fn(g, " ");
102
103 for (engine_id = 0; engine_id < f->num_engines; engine_id++) {
104 active_engine_id = f->active_engines_list[engine_id];
105 gate_ctrl = gk20a_readl(g, therm_gate_ctrl_r(active_engine_id));
106
107 if (nvgpu_platform_is_simulation(g)) {
108 gate_ctrl = set_field(gate_ctrl,
109 therm_gate_ctrl_eng_delay_after_m(),
110 therm_gate_ctrl_eng_delay_after_f(4));
111 }
112
113 /* 2 * (1 << 9) = 1024 clks */
114 gate_ctrl = set_field(gate_ctrl,
115 therm_gate_ctrl_eng_idle_filt_exp_m(),
116 therm_gate_ctrl_eng_idle_filt_exp_f(9));
117 gate_ctrl = set_field(gate_ctrl,
118 therm_gate_ctrl_eng_idle_filt_mant_m(),
119 therm_gate_ctrl_eng_idle_filt_mant_f(2));
120 gate_ctrl = set_field(gate_ctrl,
121 therm_gate_ctrl_eng_delay_before_m(),
122 therm_gate_ctrl_eng_delay_before_f(4));
123 gk20a_writel(g, therm_gate_ctrl_r(active_engine_id), gate_ctrl);
124 }
125
126 /* default fecs_idle_filter to 0 */
127 idle_filter = gk20a_readl(g, therm_fecs_idle_filter_r());
128 idle_filter &= ~therm_fecs_idle_filter_value_m();
129 gk20a_writel(g, therm_fecs_idle_filter_r(), idle_filter);
130 /* default hubmmu_idle_filter to 0 */
131 idle_filter = gk20a_readl(g, therm_hubmmu_idle_filter_r());
132 idle_filter &= ~therm_hubmmu_idle_filter_value_m();
133 gk20a_writel(g, therm_hubmmu_idle_filter_r(), idle_filter);
134
135 nvgpu_log_fn(g, "done");
136 return 0;
137}
diff --git a/drivers/gpu/nvgpu/common/therm/therm_gp10b.h b/drivers/gpu/nvgpu/common/therm/therm_gp10b.h
new file mode 100644
index 00000000..2a40b73c
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/therm/therm_gp10b.h
@@ -0,0 +1,29 @@
1/*
2 * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22#ifndef THERM_GP10B_H
23#define THERM_GP10B_H
24
25struct gk20a;
26int gp10b_init_therm_setup_hw(struct gk20a *g);
27int gp10b_elcg_init_idle_filters(struct gk20a *g);
28
29#endif /* THERM_GP10B_H */
diff --git a/drivers/gpu/nvgpu/common/therm/therm_gv11b.c b/drivers/gpu/nvgpu/common/therm/therm_gv11b.c
new file mode 100644
index 00000000..77edd7e1
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/therm/therm_gv11b.c
@@ -0,0 +1,183 @@
1/*
2 * GV11B Therm
3 *
4 * Copyright (c) 2015-2018, NVIDIA CORPORATION. All rights reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24
25#include "gk20a/gk20a.h"
26#include "therm_gv11b.h"
27
28#include <nvgpu/soc.h>
29#include <nvgpu/io.h>
30#include <nvgpu/utils.h>
31
32#include <nvgpu/hw/gv11b/hw_therm_gv11b.h>
33
34#include "therm_gv11b.h"
35
36int gv11b_init_therm_setup_hw(struct gk20a *g)
37{
38 u32 v;
39
40 nvgpu_log_fn(g, " ");
41
42 /* program NV_THERM registers */
43 gk20a_writel(g, therm_use_a_r(), therm_use_a_ext_therm_0_enable_f() |
44 therm_use_a_ext_therm_1_enable_f() |
45 therm_use_a_ext_therm_2_enable_f());
46 gk20a_writel(g, therm_evt_ext_therm_0_r(),
47 therm_evt_ext_therm_0_slow_factor_f(0x2));
48 gk20a_writel(g, therm_evt_ext_therm_1_r(),
49 therm_evt_ext_therm_1_slow_factor_f(0x6));
50 gk20a_writel(g, therm_evt_ext_therm_2_r(),
51 therm_evt_ext_therm_2_slow_factor_f(0xe));
52
53 gk20a_writel(g, therm_grad_stepping_table_r(0),
54 therm_grad_stepping_table_slowdown_factor0_f(
55 therm_grad_stepping_table_slowdown_factor0_fpdiv_by1_f()) |
56 therm_grad_stepping_table_slowdown_factor1_f(
57 therm_grad_stepping_table_slowdown_factor0_fpdiv_by1p5_f()) |
58 therm_grad_stepping_table_slowdown_factor2_f(
59 therm_grad_stepping_table_slowdown_factor0_fpdiv_by2_f()) |
60 therm_grad_stepping_table_slowdown_factor3_f(
61 therm_grad_stepping_table_slowdown_factor0_fpdiv_by4_f()) |
62 therm_grad_stepping_table_slowdown_factor4_f(
63 therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()));
64
65 gk20a_writel(g, therm_grad_stepping_table_r(1),
66 therm_grad_stepping_table_slowdown_factor0_f(
67 therm_grad_stepping_table_slowdown_factor0_fpdiv_by16_f()) |
68 therm_grad_stepping_table_slowdown_factor1_f(
69 therm_grad_stepping_table_slowdown_factor0_fpdiv_by32_f()) |
70 therm_grad_stepping_table_slowdown_factor2_f(
71 therm_grad_stepping_table_slowdown_factor0_fpdiv_by32_f()) |
72 therm_grad_stepping_table_slowdown_factor3_f(
73 therm_grad_stepping_table_slowdown_factor0_fpdiv_by32_f()) |
74 therm_grad_stepping_table_slowdown_factor4_f(
75 therm_grad_stepping_table_slowdown_factor0_fpdiv_by32_f()));
76
77 v = gk20a_readl(g, therm_clk_timing_r(0));
78 v |= therm_clk_timing_grad_slowdown_enabled_f();
79 gk20a_writel(g, therm_clk_timing_r(0), v);
80
81 v = gk20a_readl(g, therm_config2_r());
82 v |= therm_config2_grad_enable_f(1);
83 v |= therm_config2_slowdown_factor_extended_f(1);
84 v = set_field(v, therm_config2_grad_step_duration_m(),
85 therm_config2_grad_step_duration_f(0));
86 gk20a_writel(g, therm_config2_r(), v);
87
88 gk20a_writel(g, therm_grad_stepping1_r(),
89 therm_grad_stepping1_pdiv_duration_f(0xbf4));
90
91 v = gk20a_readl(g, therm_grad_stepping0_r());
92 v |= therm_grad_stepping0_feature_enable_f();
93 gk20a_writel(g, therm_grad_stepping0_r(), v);
94
95 /* disable idle clock slowdown */
96 v = therm_clk_slowdown_2_idle_condition_a_select_f(0) |
97 therm_clk_slowdown_2_idle_condition_a_type_never_f() |
98 therm_clk_slowdown_2_idle_condition_b_type_never_f();
99 gk20a_writel(g, therm_clk_slowdown_2_r(0), v);
100
101 return 0;
102}
103
104void gv11b_therm_init_elcg_mode(struct gk20a *g, u32 mode, u32 engine)
105{
106 u32 gate_ctrl;
107
108 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_ELCG))
109 return;
110
111 gate_ctrl = gk20a_readl(g, therm_gate_ctrl_r(engine));
112
113 switch (mode) {
114 case ELCG_RUN:
115 gate_ctrl = set_field(gate_ctrl,
116 therm_gate_ctrl_eng_clk_m(),
117 therm_gate_ctrl_eng_clk_run_f());
118 gate_ctrl = set_field(gate_ctrl,
119 therm_gate_ctrl_idle_holdoff_m(),
120 therm_gate_ctrl_idle_holdoff_on_f());
121 break;
122 case ELCG_STOP:
123 gate_ctrl = set_field(gate_ctrl,
124 therm_gate_ctrl_eng_clk_m(),
125 therm_gate_ctrl_eng_clk_stop_f());
126 break;
127 case ELCG_AUTO:
128 gate_ctrl = set_field(gate_ctrl,
129 therm_gate_ctrl_eng_clk_m(),
130 therm_gate_ctrl_eng_clk_auto_f());
131 break;
132 default:
133 nvgpu_err(g, "invalid elcg mode %d", mode);
134 }
135
136 gk20a_writel(g, therm_gate_ctrl_r(engine), gate_ctrl);
137}
138
139int gv11b_elcg_init_idle_filters(struct gk20a *g)
140{
141 u32 gate_ctrl, idle_filter;
142 u32 engine_id;
143 u32 active_engine_id = 0;
144 struct fifo_gk20a *f = &g->fifo;
145
146 if (nvgpu_platform_is_simulation(g))
147 return 0;
148
149 nvgpu_log_info(g, "init clock/power gate reg");
150
151 for (engine_id = 0; engine_id < f->num_engines; engine_id++) {
152 active_engine_id = f->active_engines_list[engine_id];
153
154 gate_ctrl = gk20a_readl(g, therm_gate_ctrl_r(active_engine_id));
155 gate_ctrl = set_field(gate_ctrl,
156 therm_gate_ctrl_eng_idle_filt_exp_m(),
157 therm_gate_ctrl_eng_idle_filt_exp__prod_f());
158 gate_ctrl = set_field(gate_ctrl,
159 therm_gate_ctrl_eng_idle_filt_mant_m(),
160 therm_gate_ctrl_eng_idle_filt_mant__prod_f());
161 gate_ctrl = set_field(gate_ctrl,
162 therm_gate_ctrl_eng_delay_before_m(),
163 therm_gate_ctrl_eng_delay_before__prod_f());
164 gate_ctrl = set_field(gate_ctrl,
165 therm_gate_ctrl_eng_delay_after_m(),
166 therm_gate_ctrl_eng_delay_after__prod_f());
167 gk20a_writel(g, therm_gate_ctrl_r(active_engine_id), gate_ctrl);
168 }
169
170 idle_filter = gk20a_readl(g, therm_fecs_idle_filter_r());
171 idle_filter = set_field(idle_filter,
172 therm_fecs_idle_filter_value_m(),
173 therm_fecs_idle_filter_value__prod_f());
174 gk20a_writel(g, therm_fecs_idle_filter_r(), idle_filter);
175
176 idle_filter = gk20a_readl(g, therm_hubmmu_idle_filter_r());
177 idle_filter = set_field(idle_filter,
178 therm_hubmmu_idle_filter_value_m(),
179 therm_hubmmu_idle_filter_value__prod_f());
180 gk20a_writel(g, therm_hubmmu_idle_filter_r(), idle_filter);
181
182 return 0;
183}
diff --git a/drivers/gpu/nvgpu/common/therm/therm_gv11b.h b/drivers/gpu/nvgpu/common/therm/therm_gv11b.h
new file mode 100644
index 00000000..7058af9f
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/therm/therm_gv11b.h
@@ -0,0 +1,30 @@
1/*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22#ifndef THERM_GV11B_H
23#define THERM_GV11B_H
24
25struct gk20a;
26int gv11b_elcg_init_idle_filters(struct gk20a *g);
27int gv11b_init_therm_setup_hw(struct gk20a *g);
28void gv11b_therm_init_elcg_mode(struct gk20a *g, u32 mode, u32 engine);
29
30#endif /* THERM_GV11B_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-04 19:36:09 -0400