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author | Deepak Nibade <dnibade@nvidia.com> | 2018-09-19 09:44:25 -0400 |
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committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-09-24 13:15:14 -0400 |
commit | b7b107c1a19d0c9ca399c6a356a9d1adc4daac85 (patch) | |
tree | b733aaf34a2bf3fbb58c322d73fec7036276110c /drivers/gpu/nvgpu/common/sim.c | |
parent | e16843c2efdffa13c15cc0a014b2a5598cc2f4ec (diff) |
gpu: nvgpu: Add HALs to implement pdb cache WAR
We have a h/w bug on some chips and we need to support below additional
HALs to implement a s/w WAR
gops.fifo.init_pdb_cache_war()
gops.fifo.deinit_pdb_cache_war()
gops.fb.apply_pdb_cache_war()
Add new API nvgpu_init_mm_pdb_cache_war() to initialize WAR sequence
and call this from MM initialization and before setting up rest of the
memory management units
Deinitialize WAR while cleaning up MM support
Add pdb_cache_war_mem member to gk20a to hold all the memory needed
for the WAR
Bug 200449545
Change-Id: Id2ac0d940c7881c7b0cf396413273c0f329a1a1f
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1834901
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/common/sim.c')
0 files changed, 0 insertions, 0 deletions