diff options
author | Deepak Nibade <dnibade@nvidia.com> | 2017-01-24 08:30:42 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-02-22 07:15:02 -0500 |
commit | 8ee3aa4b3175d8d27e57a0f5d5e2cdf3d78a4a58 (patch) | |
tree | 505dfd2ea2aca2f1cbdb254baee980862d21e04d /drivers/gpu/nvgpu/common/semaphore.c | |
parent | 1f855af63fdd31fe3dcfee75f4f5f9b62f30d87e (diff) |
gpu: nvgpu: use common nvgpu mutex/spinlock APIs
Instead of using Linux APIs for mutex and spinlocks
directly, use new APIs defined in <nvgpu/lock.h>
Replace Linux specific mutex/spinlock declaration,
init, lock, unlock APIs with new APIs
e.g
struct mutex is replaced by struct nvgpu_mutex and
mutex_lock() is replaced by nvgpu_mutex_acquire()
And also include <nvgpu/lock.h> instead of including
<linux/mutex.h> and <linux/spinlock.h>
Add explicit nvgpu/lock.h includes to below
files to fix complilation failures.
gk20a/platform_gk20a.h
include/nvgpu/allocator.h
Jira NVGPU-13
Change-Id: I81a05d21ecdbd90c2076a9f0aefd0e40b215bd33
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1293187
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/common/semaphore.c')
-rw-r--r-- | drivers/gpu/nvgpu/common/semaphore.c | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/drivers/gpu/nvgpu/common/semaphore.c b/drivers/gpu/nvgpu/common/semaphore.c index 4bf8695d..919f26ec 100644 --- a/drivers/gpu/nvgpu/common/semaphore.c +++ b/drivers/gpu/nvgpu/common/semaphore.c | |||
@@ -24,13 +24,13 @@ | |||
24 | #define __lock_sema_sea(s) \ | 24 | #define __lock_sema_sea(s) \ |
25 | do { \ | 25 | do { \ |
26 | gpu_sema_verbose_dbg("Acquiring sema lock..."); \ | 26 | gpu_sema_verbose_dbg("Acquiring sema lock..."); \ |
27 | mutex_lock(&s->sea_lock); \ | 27 | nvgpu_mutex_acquire(&s->sea_lock); \ |
28 | gpu_sema_verbose_dbg("Sema lock aquried!"); \ | 28 | gpu_sema_verbose_dbg("Sema lock aquried!"); \ |
29 | } while (0) | 29 | } while (0) |
30 | 30 | ||
31 | #define __unlock_sema_sea(s) \ | 31 | #define __unlock_sema_sea(s) \ |
32 | do { \ | 32 | do { \ |
33 | mutex_unlock(&s->sea_lock); \ | 33 | nvgpu_mutex_release(&s->sea_lock); \ |
34 | gpu_sema_verbose_dbg("Released sema lock"); \ | 34 | gpu_sema_verbose_dbg("Released sema lock"); \ |
35 | } while (0) | 35 | } while (0) |
36 | 36 | ||
@@ -81,7 +81,7 @@ struct nvgpu_semaphore_sea *nvgpu_semaphore_sea_create(struct gk20a *g) | |||
81 | g->sema_sea->page_count = 0; | 81 | g->sema_sea->page_count = 0; |
82 | g->sema_sea->gk20a = g; | 82 | g->sema_sea->gk20a = g; |
83 | INIT_LIST_HEAD(&g->sema_sea->pool_list); | 83 | INIT_LIST_HEAD(&g->sema_sea->pool_list); |
84 | mutex_init(&g->sema_sea->sea_lock); | 84 | nvgpu_mutex_init(&g->sema_sea->sea_lock); |
85 | 85 | ||
86 | if (__nvgpu_semaphore_sea_grow(g->sema_sea)) | 86 | if (__nvgpu_semaphore_sea_grow(g->sema_sea)) |
87 | goto cleanup; | 87 | goto cleanup; |
@@ -138,7 +138,7 @@ struct nvgpu_semaphore_pool *nvgpu_semaphore_pool_alloc( | |||
138 | p->sema_sea = sea; | 138 | p->sema_sea = sea; |
139 | INIT_LIST_HEAD(&p->hw_semas); | 139 | INIT_LIST_HEAD(&p->hw_semas); |
140 | kref_init(&p->ref); | 140 | kref_init(&p->ref); |
141 | mutex_init(&p->pool_lock); | 141 | nvgpu_mutex_init(&p->pool_lock); |
142 | 142 | ||
143 | sea->page_count++; | 143 | sea->page_count++; |
144 | list_add(&p->pool_list_entry, &sea->pool_list); | 144 | list_add(&p->pool_list_entry, &sea->pool_list); |
@@ -344,7 +344,7 @@ static int __nvgpu_init_hw_sema(struct channel_gk20a *ch) | |||
344 | 344 | ||
345 | BUG_ON(!p); | 345 | BUG_ON(!p); |
346 | 346 | ||
347 | mutex_lock(&p->pool_lock); | 347 | nvgpu_mutex_acquire(&p->pool_lock); |
348 | 348 | ||
349 | /* Find an available HW semaphore. */ | 349 | /* Find an available HW semaphore. */ |
350 | hw_sema_idx = __semaphore_bitmap_alloc(p->semas_alloced, | 350 | hw_sema_idx = __semaphore_bitmap_alloc(p->semas_alloced, |
@@ -371,14 +371,14 @@ static int __nvgpu_init_hw_sema(struct channel_gk20a *ch) | |||
371 | 371 | ||
372 | list_add(&hw_sema->hw_sema_list, &p->hw_semas); | 372 | list_add(&hw_sema->hw_sema_list, &p->hw_semas); |
373 | 373 | ||
374 | mutex_unlock(&p->pool_lock); | 374 | nvgpu_mutex_release(&p->pool_lock); |
375 | 375 | ||
376 | return 0; | 376 | return 0; |
377 | 377 | ||
378 | fail_free_idx: | 378 | fail_free_idx: |
379 | clear_bit(hw_sema_idx, p->semas_alloced); | 379 | clear_bit(hw_sema_idx, p->semas_alloced); |
380 | fail: | 380 | fail: |
381 | mutex_unlock(&p->pool_lock); | 381 | nvgpu_mutex_release(&p->pool_lock); |
382 | return ret; | 382 | return ret; |
383 | } | 383 | } |
384 | 384 | ||
@@ -391,7 +391,7 @@ void nvgpu_semaphore_free_hw_sema(struct channel_gk20a *ch) | |||
391 | 391 | ||
392 | BUG_ON(!p); | 392 | BUG_ON(!p); |
393 | 393 | ||
394 | mutex_lock(&p->pool_lock); | 394 | nvgpu_mutex_acquire(&p->pool_lock); |
395 | 395 | ||
396 | clear_bit(ch->hw_sema->idx, p->semas_alloced); | 396 | clear_bit(ch->hw_sema->idx, p->semas_alloced); |
397 | 397 | ||
@@ -400,7 +400,7 @@ void nvgpu_semaphore_free_hw_sema(struct channel_gk20a *ch) | |||
400 | kfree(ch->hw_sema); | 400 | kfree(ch->hw_sema); |
401 | ch->hw_sema = NULL; | 401 | ch->hw_sema = NULL; |
402 | 402 | ||
403 | mutex_unlock(&p->pool_lock); | 403 | nvgpu_mutex_release(&p->pool_lock); |
404 | } | 404 | } |
405 | 405 | ||
406 | /* | 406 | /* |