gpu: nvgpu: common: Fix MISRA 15.6 violations

MISRA Rule-15.6 requires that all if-else blocks be enclosed in braces,
including single statement blocks. Fix errors due to single statement
if blocks without braces, introducing the braces.

JIRA NVGPU-671

Change-Id: I4d9933c51a297a725f48cbb15520a70494d74aeb
Signed-off-by: Srirangan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1800833
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

2 files changed, 7 insertions, 4 deletions

diff --git a/drivers/gpu/nvgpu/common/ptimer/ptimer.c b/drivers/gpu/nvgpu/common/ptimer/ptimer.c
index d5f9470d..3f3a5f9b 100644
--- a/drivers/gpu/nvgpu/common/ptimer/ptimer.c
+++ b/drivers/gpu/nvgpu/common/ptimer/ptimer.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -39,8 +39,9 @@ int nvgpu_get_timestamps_zipper(struct gk20a *g,
 
         for (i = 0; i < count; i++) {
                 err = g->ops.ptimer.read_ptimer(g, &samples[i].gpu_timestamp);
-                if (err)
+                if (err) {
                         return err;
+                }
 
                 samples[i].cpu_timestamp = nvgpu_hr_timestamp();
         }
diff --git a/drivers/gpu/nvgpu/common/ptimer/ptimer_gk20a.c b/drivers/gpu/nvgpu/common/ptimer/ptimer_gk20a.c
index 0b3188ee..a9c971df 100644
--- a/drivers/gpu/nvgpu/common/ptimer/ptimer_gk20a.c
+++ b/drivers/gpu/nvgpu/common/ptimer/ptimer_gk20a.c
@@ -54,9 +54,10 @@ void gk20a_ptimer_isr(struct gk20a *g)
 
         if (fecs_errcode) {
                 nvgpu_err(g, "FECS_ERRCODE 0x%08x", fecs_errcode);
-                if (g->ops.priv_ring.decode_error_code)
+                if (g->ops.priv_ring.decode_error_code) {
                         g->ops.priv_ring.decode_error_code(g,
                                                 fecs_errcode);
+                }
         }
 }
 
@@ -66,8 +67,9 @@ int gk20a_read_ptimer(struct gk20a *g, u64 *value)
         unsigned int i = 0;
         u32 gpu_timestamp_hi_prev = 0;
 
-        if (!value)
+        if (!value) {
                 return -EINVAL;
+        }
 
         /* Note. The GPU nanosecond timer consists of two 32-bit
          * registers (high & low). To detect a possible low register