gpu: nvgpu: PMU super surface support

- Added ops "pmu.alloc_super_surface" to create
  memory space for pmu super surface
- Defined method nvgpu_pmu_sysmem_surface_alloc()
  to allocate pmu super surface memory & assigned
  to "pmu.alloc_super_surface" for gv100
- "pmu.alloc_super_surface" set to NULL for gp106
- Memory space of size "struct nv_pmu_super_surface"
  is allocated during pmu sw init setup if
  "pmu.alloc_super_surface" is not NULL &
  free if error occur.
- Added ops "pmu_ver.config_pmu_cmdline_args_super_surface"
  to describe PMU super surface details to PMU ucode
  as part of pmu command line args command if
  "pmu.alloc_super_surface" is not NULL.
- Updated pmu_cmdline_args_v6 to include member
  "struct flcn_mem_desc_v0 super_surface"
- Free allocated memory for PMU super surface in
  nvgpu_remove_pmu_support() method
- Added "struct nvgpu_mem super_surface_buf" to "nvgpu_pmu" struct
- Created header file "gpmu_super_surf_if.h" to include interface
  about pmu super surface, added "struct nv_pmu_super_surface"
  to hold super surface members along with rsvd[x] dummy space
  to sync members offset with PMU super surface members.

Change-Id: I2b28912bf4d86a8cc72884e3b023f21c73fb3503
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1656571
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

2 files changed, 43 insertions, 1 deletions

diff --git a/drivers/gpu/nvgpu/common/pmu/pmu.c b/drivers/gpu/nvgpu/common/pmu/pmu.c
index e96ea090..aaae138c 100644
--- a/drivers/gpu/nvgpu/common/pmu/pmu.c
+++ b/drivers/gpu/nvgpu/common/pmu/pmu.c
@@ -241,11 +241,19 @@ static int nvgpu_init_pmu_setup_sw(struct gk20a *g)
 
         pmu->seq_buf.size = GK20A_PMU_SEQ_BUF_SIZE;
 
+        if (g->ops.pmu.alloc_super_surface) {
+                err = g->ops.pmu.alloc_super_surface(g,
+                                &pmu->super_surface_buf,
+                                sizeof(struct nv_pmu_super_surface));
+                if (err)
+                        goto err_free_seq_buf;
+        }
+
         err = nvgpu_dma_alloc_map(vm, GK20A_PMU_TRACE_BUFSIZE,
                         &pmu->trace_buf);
         if (err) {
                 nvgpu_err(g, "failed to allocate pmu trace buffer\n");
-                goto err_free_seq_buf;
+                goto err_free_super_surface;
         }
 
         pmu->sw_ready = true;
@@ -253,6 +261,9 @@ static int nvgpu_init_pmu_setup_sw(struct gk20a *g)
 skip_init:
         nvgpu_log_fn(g, "done");
         return 0;
+ err_free_super_surface:
+         if (g->ops.pmu.alloc_super_surface)
+                 nvgpu_dma_unmap_free(vm, &pmu->super_surface_buf);
  err_free_seq_buf:
         nvgpu_dma_unmap_free(vm, &pmu->seq_buf);
  err_free_seq:
@@ -560,6 +571,23 @@ int nvgpu_pmu_sysmem_surface_alloc(struct gk20a *g, struct nvgpu_mem *mem,
         return 0;
 }
 
+int nvgpu_pmu_super_surface_alloc(struct gk20a *g,
+        struct nvgpu_mem *mem_surface, u32 size)
+{
+        struct vm_gk20a *vm = g->mm.pmu.vm;
+        int err = 0;
+
+        nvgpu_log_fn(g, " ");
+
+        err = nvgpu_dma_alloc_map(vm, size, mem_surface);
+        if (err) {
+                nvgpu_err(g, "failed to allocate pmu suffer surface\n");
+                err = -ENOMEM;
+        }
+
+        return err;
+}
+
 void nvgpu_pmu_surface_free(struct gk20a *g, struct nvgpu_mem *mem)
 {
         nvgpu_dma_free(g, mem);
diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_fw.c b/drivers/gpu/nvgpu/common/pmu/pmu_fw.c
index 549cfdc6..6b565abb 100644
--- a/drivers/gpu/nvgpu/common/pmu/pmu_fw.c
+++ b/drivers/gpu/nvgpu/common/pmu/pmu_fw.c
@@ -142,6 +142,16 @@ static void set_pmu_cmdline_args_falctracedmabase_v5(struct nvgpu_pmu *pmu)
         nvgpu_pmu_surface_describe(g, &pmu->trace_buf, &pmu->args_v5.trace_buf);
 }
 
+static void config_pmu_cmdline_args_super_surface_v6(struct nvgpu_pmu *pmu)
+{
+        struct gk20a *g = gk20a_from_pmu(pmu);
+
+        if (g->ops.pmu.alloc_super_surface) {
+                nvgpu_pmu_surface_describe(g, &pmu->super_surface_buf,
+                        &pmu->args_v6.super_surface);
+        }
+}
+
 static void set_pmu_cmdline_args_falctracedmaidx_v5(
                         struct nvgpu_pmu *pmu, u32 idx)
 {
@@ -1250,6 +1260,8 @@ static int nvgpu_init_pmu_fw_ver_ops(struct nvgpu_pmu *pmu)
                         set_pmu_cmdline_args_falctracedmabase_v5;
                 g->ops.pmu_ver.set_pmu_cmdline_args_trace_dma_idx =
                         set_pmu_cmdline_args_falctracedmaidx_v5;
+                g->ops.pmu_ver.config_pmu_cmdline_args_super_surface =
+                        config_pmu_cmdline_args_super_surface_v6;
                 g->ops.pmu_ver.get_pmu_cmdline_args_ptr =
                         get_pmu_cmdline_args_ptr_v5;
                 g->ops.pmu_ver.get_pmu_allocation_struct_size =
@@ -1587,6 +1599,8 @@ static void nvgpu_remove_pmu_support(struct nvgpu_pmu *pmu)
 
         nvgpu_dma_unmap_free(vm, &pmu->seq_buf);
 
+        nvgpu_dma_unmap_free(vm, &pmu->super_surface_buf);
+
         nvgpu_mutex_destroy(&pmu->elpg_mutex);
         nvgpu_mutex_destroy(&pmu->pg_mutex);
         nvgpu_mutex_destroy(&pmu->isr_mutex);