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authorDebarshi Dutta <ddutta@nvidia.com>2019-04-30 04:24:08 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2019-05-09 17:41:30 -0400
commitc81cc032c48a1b25e095b17b77399166c9091ff3 (patch)
treeace7d238c55bbb5e96fb6fd74deb156f3c513bae /drivers/gpu/nvgpu/common/pmu
parentf495f52c70c6bd7b7a4e6897270e4696efa57d5c (diff)
gpu: nvgpu: add cg and pg function
Add new power/clock gating functions that can be called by other units. New clock_gating functions will reside in cg.c under common/power_features/cg unit. New power gating functions will reside in pg.c under common/power_features/pg unit. Use nvgpu_pg_elpg_disable and nvgpu_pg_elpg_enable to disable/enable elpg and also in gr_gk20a_elpg_protected macro to access gr registers. Add cg_pg_lock to make elpg_enabled, elcg_enabled, blcg_enabled and slcg_enabled thread safe. JIRA NVGPU-2014 Change-Id: I00d124c2ee16242c9a3ef82e7620fbb7f1297aff Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2025493 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> (cherry-picked from c90585856567a547173a8b207365b3a4a3ccdd57 in dev-kernel) Reviewed-on: https://git-master.nvidia.com/r/2108406 GVS: Gerrit_Virtual_Submit Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/common/pmu')
-rw-r--r--drivers/gpu/nvgpu/common/pmu/pmu.c14
1 files changed, 5 insertions, 9 deletions
diff --git a/drivers/gpu/nvgpu/common/pmu/pmu.c b/drivers/gpu/nvgpu/common/pmu/pmu.c
index f86dc2c2..b9cfd033 100644
--- a/drivers/gpu/nvgpu/common/pmu/pmu.c
+++ b/drivers/gpu/nvgpu/common/pmu/pmu.c
@@ -30,6 +30,8 @@
30#include <nvgpu/bug.h> 30#include <nvgpu/bug.h>
31#include <nvgpu/utils.h> 31#include <nvgpu/utils.h>
32#include <nvgpu/gk20a.h> 32#include <nvgpu/gk20a.h>
33#include <nvgpu/power_features/cg.h>
34
33 35
34static int nvgpu_pg_init_task(void *arg); 36static int nvgpu_pg_init_task(void *arg);
35 37
@@ -44,15 +46,9 @@ static int pmu_enable_hw(struct nvgpu_pmu *pmu, bool enable)
44 /* bring PMU falcon/engine out of reset */ 46 /* bring PMU falcon/engine out of reset */
45 g->ops.pmu.reset_engine(g, true); 47 g->ops.pmu.reset_engine(g, true);
46 48
47 if (g->ops.clock_gating.slcg_pmu_load_gating_prod) { 49 nvgpu_cg_slcg_pmu_load_enable(g);
48 g->ops.clock_gating.slcg_pmu_load_gating_prod(g,
49 g->slcg_enabled);
50 }
51 50
52 if (g->ops.clock_gating.blcg_pmu_load_gating_prod) { 51 nvgpu_cg_blcg_pmu_load_enable(g);
53 g->ops.clock_gating.blcg_pmu_load_gating_prod(g,
54 g->blcg_enabled);
55 }
56 52
57 if (nvgpu_flcn_mem_scrub_wait(pmu->flcn)) { 53 if (nvgpu_flcn_mem_scrub_wait(pmu->flcn)) {
58 /* keep PMU falcon/engine in reset 54 /* keep PMU falcon/engine in reset
@@ -446,7 +442,7 @@ static void pmu_setup_hw_enable_elpg(struct gk20a *g)
446 g->ops.gr.pmu_save_zbc(g, 0xf); 442 g->ops.gr.pmu_save_zbc(g, 0xf);
447 } 443 }
448 444
449 if (g->elpg_enabled) { 445 if (g->can_elpg && g->elpg_enabled) {
450 /* Init reg with prod values*/ 446 /* Init reg with prod values*/
451 if (g->ops.pmu.pmu_setup_elpg) { 447 if (g->ops.pmu.pmu_setup_elpg) {
452 g->ops.pmu.pmu_setup_elpg(g); 448 g->ops.pmu.pmu_setup_elpg(g);