diff options
author | Vaikundanathan S <vaikuns@nvidia.com> | 2018-08-28 02:28:25 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-09-20 13:50:53 -0400 |
commit | ae809fddbe90bcec0d48e1213fa36cc5ba76550d (patch) | |
tree | bbafc71a543abf4b02e76290d058719f27f5f3b8 /drivers/gpu/nvgpu/common/pmu | |
parent | 85c323c3e89d6e1b624b839c3325ae072952e545 (diff) |
gpu:nvgpu: Add GV10x perf event
In case of VFE update, schedule work to set P0 clocks.
Added function nvgpu_clk_set_fll_clk_gv10x to update P0 clocks on perf event.
Fixed MISRA issues caused by this excluding external functions and MACROs
Bug 2331655
Change-Id: Id96c473092ee7f0b651413aefdd4b6f2f59e0b12
Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1808014
Reviewed-on: https://git-master.nvidia.com/r/1813881
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/common/pmu')
-rw-r--r-- | drivers/gpu/nvgpu/common/pmu/pmu_fw.c | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_fw.c b/drivers/gpu/nvgpu/common/pmu/pmu_fw.c index a94453fb..c2d6a921 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu_fw.c +++ b/drivers/gpu/nvgpu/common/pmu/pmu_fw.c | |||
@@ -1325,8 +1325,6 @@ static int nvgpu_init_pmu_fw_ver_ops(struct nvgpu_pmu *pmu) | |||
1325 | clk_avfs_get_vin_cal_fuse_v20; | 1325 | clk_avfs_get_vin_cal_fuse_v20; |
1326 | g->ops.pmu_ver.clk.clk_vf_change_inject_data_fill = | 1326 | g->ops.pmu_ver.clk.clk_vf_change_inject_data_fill = |
1327 | nvgpu_clk_vf_change_inject_data_fill_gv10x; | 1327 | nvgpu_clk_vf_change_inject_data_fill_gv10x; |
1328 | g->ops.pmu_ver.clk.perf_pmu_vfe_load = | ||
1329 | perf_pmu_vfe_load_gv10x; | ||
1330 | g->ops.pmu_ver.clk.clk_set_boot_clk = | 1328 | g->ops.pmu_ver.clk.clk_set_boot_clk = |
1331 | nvgpu_clk_set_boot_fll_clk_gv10x; | 1329 | nvgpu_clk_set_boot_fll_clk_gv10x; |
1332 | } else { | 1330 | } else { |
@@ -1500,8 +1498,6 @@ static int nvgpu_init_pmu_fw_ver_ops(struct nvgpu_pmu *pmu) | |||
1500 | clk_avfs_get_vin_cal_fuse_v10; | 1498 | clk_avfs_get_vin_cal_fuse_v10; |
1501 | g->ops.pmu_ver.clk.clk_vf_change_inject_data_fill = | 1499 | g->ops.pmu_ver.clk.clk_vf_change_inject_data_fill = |
1502 | nvgpu_clk_vf_change_inject_data_fill_gp10x; | 1500 | nvgpu_clk_vf_change_inject_data_fill_gp10x; |
1503 | g->ops.pmu_ver.clk.perf_pmu_vfe_load = | ||
1504 | perf_pmu_vfe_load; | ||
1505 | break; | 1501 | break; |
1506 | case APP_VERSION_GM20B: | 1502 | case APP_VERSION_GM20B: |
1507 | g->ops.pmu_ver.pg_cmd_eng_buf_load_size = | 1503 | g->ops.pmu_ver.pg_cmd_eng_buf_load_size = |