nvgpu: common: MISRA 10.1 boolean fixes

Fix violations where a variable of type non-boolean is used as a
boolean in gpu/nvgpu/common.

JIRA NVGPU-646

Change-Id: I9773d863b715f83ae1772b75d5373f77244bc8ca
Signed-off-by: Amulya <Amurthyreddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1807132
GVS: Gerrit_Virtual_Submit
Tested-by: Amulya Murthyreddy <amurthyreddy@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

5 files changed, 45 insertions, 44 deletions

diff --git a/drivers/gpu/nvgpu/common/pmu/pmu.c b/drivers/gpu/nvgpu/common/pmu/pmu.c
index 0395e463..6d1d5f00 100644
--- a/drivers/gpu/nvgpu/common/pmu/pmu.c
+++ b/drivers/gpu/nvgpu/common/pmu/pmu.c
@@ -170,8 +170,8 @@ void nvgpu_kill_task_pg_init(struct gk20a *g)
                                 break;
                         }
                         nvgpu_udelay(2);
-                } while (!nvgpu_timeout_expired_msg(&timeout,
-                        "timeout - waiting PMU state machine thread stop"));
+                } while (nvgpu_timeout_expired_msg(&timeout,
+                        "timeout - waiting PMU state machine thread stop") == 0);
         }
 }
 
@@ -214,7 +214,7 @@ static int nvgpu_init_pmu_setup_sw(struct gk20a *g)
         pmu->mutex_cnt = g->ops.pmu.pmu_mutex_size();
         pmu->mutex = nvgpu_kzalloc(g, pmu->mutex_cnt *
                 sizeof(struct pmu_mutex));
-        if (!pmu->mutex) {
+        if (pmu->mutex == NULL) {
                 err = -ENOMEM;
                 goto err;
         }
@@ -226,7 +226,7 @@ static int nvgpu_init_pmu_setup_sw(struct gk20a *g)
 
         pmu->seq = nvgpu_kzalloc(g, PMU_MAX_NUM_SEQUENCES *
                 sizeof(struct pmu_sequence));
-        if (!pmu->seq) {
+        if (pmu->seq == NULL) {
                 err = -ENOMEM;
                 goto err_free_mutex;
         }
diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_fw.c b/drivers/gpu/nvgpu/common/pmu/pmu_fw.c
index bf54e0d6..a94453fb 100644
--- a/drivers/gpu/nvgpu/common/pmu/pmu_fw.c
+++ b/drivers/gpu/nvgpu/common/pmu/pmu_fw.c
@@ -1738,12 +1738,12 @@ int nvgpu_pmu_prepare_ns_ucode_blob(struct gk20a *g)
 
         nvgpu_log_fn(g, " ");
 
-        if (pmu->fw) {
+        if (pmu->fw != NULL) {
                 return nvgpu_init_pmu_fw_support(pmu);
         }
 
         pmu->fw = nvgpu_request_firmware(g, NVGPU_PMU_NS_UCODE_IMAGE, 0);
-        if (!pmu->fw) {
+        if (pmu->fw == NULL) {
                 nvgpu_err(g, "failed to load pmu ucode!!");
                 return err;
         }
diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_ipc.c b/drivers/gpu/nvgpu/common/pmu/pmu_ipc.c
index 9fe999ae..6f88260f 100644
--- a/drivers/gpu/nvgpu/common/pmu/pmu_ipc.c
+++ b/drivers/gpu/nvgpu/common/pmu/pmu_ipc.c
@@ -221,7 +221,7 @@ invalid_cmd:
                 "payload in=%p, in_size=%d, in_offset=%d,\n"
                 "payload out=%p, out_size=%d, out_offset=%d",
                 queue_id, cmd->hdr.size, cmd->hdr.unit_id,
-                msg, msg ? msg->hdr.unit_id : ~0,
+                msg, (msg != NULL) ? msg->hdr.unit_id : ~0,
                 &payload->in, payload->in.size, payload->in.offset,
                 &payload->out, payload->out.size, payload->out.offset);
 
@@ -243,7 +243,7 @@ static int pmu_write_cmd(struct nvgpu_pmu *pmu, struct pmu_cmd *cmd,
 
         do {
                 err = nvgpu_flcn_queue_push(pmu->flcn, queue, cmd, cmd->hdr.size);
-                if (err == -EAGAIN && !nvgpu_timeout_expired(&timeout)) {
+                if (err == -EAGAIN && nvgpu_timeout_expired(&timeout) == 0) {
                         nvgpu_usleep_range(1000, 2000);
                 } else {
                         break;
@@ -273,7 +273,7 @@ static int pmu_cmd_payload_extract_rpc(struct gk20a *g, struct pmu_cmd *cmd,
         dmem_alloc_size = payload->rpc.size_rpc +
                 payload->rpc.size_scratch;
         dmem_alloc_offset = nvgpu_alloc(&pmu->dmem, dmem_alloc_size);
-        if (!dmem_alloc_offset) {
+        if (dmem_alloc_offset == 0U) {
                 err = -ENOMEM;
                 goto clean_up;
         }
@@ -312,11 +312,11 @@ static int pmu_cmd_payload_extract(struct gk20a *g, struct pmu_cmd *cmd,
 
         nvgpu_log_fn(g, " ");
 
-        if (payload) {
+        if (payload != NULL) {
                 seq->out_payload = payload->out.buf;
         }
 
-        if (payload && payload->in.offset != 0U) {
+        if (payload != NULL && payload->in.offset != 0U) {
                 pv->set_pmu_allocation_ptr(pmu, &in,
                 ((u8 *)&cmd->cmd + payload->in.offset));
 
@@ -331,14 +331,14 @@ static int pmu_cmd_payload_extract(struct gk20a *g, struct pmu_cmd *cmd,
                 *(pv->pmu_allocation_get_dmem_offset_addr(pmu, in)) =
                         nvgpu_alloc(&pmu->dmem,
                                 pv->pmu_allocation_get_dmem_size(pmu, in));
-                if (!*(pv->pmu_allocation_get_dmem_offset_addr(pmu, in))) {
+                if (*(pv->pmu_allocation_get_dmem_offset_addr(pmu, in)) == 0U) {
                         goto clean_up;
                 }
 
                 if (payload->in.fb_size != 0x0U) {
                         seq->in_mem = nvgpu_kzalloc(g,
                                         sizeof(struct nvgpu_mem));
-                        if (!seq->in_mem) {
+                        if (seq->in_mem == NULL) {
                                 err = -ENOMEM;
                                 goto clean_up;
                         }
@@ -365,7 +365,7 @@ static int pmu_cmd_payload_extract(struct gk20a *g, struct pmu_cmd *cmd,
                 pv->pmu_allocation_get_dmem_offset(pmu, in));
         }
 
-        if (payload && payload->out.offset != 0U) {
+        if (payload != NULL && payload->out.offset != 0U) {
                 pv->set_pmu_allocation_ptr(pmu, &out,
                 ((u8 *)&cmd->cmd + payload->out.offset));
                 pv->pmu_allocation_set_dmem_size(pmu, out,
@@ -376,15 +376,15 @@ static int pmu_cmd_payload_extract(struct gk20a *g, struct pmu_cmd *cmd,
                                 nvgpu_alloc(&pmu->dmem,
                                         pv->pmu_allocation_get_dmem_size(pmu,
                                         out));
-                        if (!*(pv->pmu_allocation_get_dmem_offset_addr(pmu,
-                                        out))) {
+                        if (*(pv->pmu_allocation_get_dmem_offset_addr(pmu,
+                                        out)) == 0U) {
                                 goto clean_up;
                         }
 
                         if (payload->out.fb_size != 0x0U) {
                                 seq->out_mem = nvgpu_kzalloc(g,
                                         sizeof(struct nvgpu_mem));
-                                if (!seq->out_mem) {
+                                if (seq->out_mem == NULL) {
                                         err = -ENOMEM;
                                         goto clean_up;
                                 }
@@ -439,16 +439,16 @@ int nvgpu_pmu_cmd_post(struct gk20a *g, struct pmu_cmd *cmd,
 
         nvgpu_log_fn(g, " ");
 
-        if ((!cmd) || (!seq_desc) || (!pmu->pmu_ready)) {
-                if (!cmd) {
+        if (cmd == NULL || seq_desc == NULL || !pmu->pmu_ready) {
+                if (cmd == NULL) {
                         nvgpu_warn(g, "%s(): PMU cmd buffer is NULL", __func__);
-                } else if (!seq_desc) {
+                } else if (seq_desc == NULL) {
                         nvgpu_warn(g, "%s(): Seq descriptor is NULL", __func__);
                 } else {
                         nvgpu_warn(g, "%s(): PMU is not ready", __func__);
                 }
 
-                WARN_ON(1);
+                WARN_ON(true);
                 return -EINVAL;
         }
 
@@ -612,7 +612,7 @@ static int pmu_handle_event(struct nvgpu_pmu *pmu, struct pmu_msg *msg)
                         err = g->ops.perf.handle_pmu_perf_event(g,
                                 (void *)&msg->msg.perf);
                 } else {
-                        WARN_ON(1);
+                        WARN_ON(true);
                 }
                 break;
         case PMU_UNIT_THERM:
@@ -641,7 +641,7 @@ static bool pmu_read_message(struct nvgpu_pmu *pmu,
 
         err = nvgpu_flcn_queue_pop(pmu->flcn, queue, &msg->hdr,
                         PMU_MSG_HDR_SIZE, &bytes_read);
-        if (err || bytes_read != PMU_MSG_HDR_SIZE) {
+        if (err != 0 || bytes_read != PMU_MSG_HDR_SIZE) {
                 nvgpu_err(g, "fail to read msg from queue %d", queue->id);
                 *status = err | -EINVAL;
                 goto clean_up;
@@ -657,7 +657,7 @@ static bool pmu_read_message(struct nvgpu_pmu *pmu,
                 /* read again after rewind */
                 err = nvgpu_flcn_queue_pop(pmu->flcn, queue, &msg->hdr,
                                 PMU_MSG_HDR_SIZE, &bytes_read);
-                if (err || bytes_read != PMU_MSG_HDR_SIZE) {
+                if (err != 0 || bytes_read != PMU_MSG_HDR_SIZE) {
                         nvgpu_err(g,
                                 "fail to read msg from queue %d", queue->id);
                         *status = err | -EINVAL;
@@ -676,7 +676,7 @@ static bool pmu_read_message(struct nvgpu_pmu *pmu,
                 read_size = msg->hdr.size - PMU_MSG_HDR_SIZE;
                 err = nvgpu_flcn_queue_pop(pmu->flcn, queue, &msg->msg,
                         read_size, &bytes_read);
-                if (err || bytes_read != read_size) {
+                if (err != 0 || bytes_read != read_size) {
                         nvgpu_err(g,
                                 "fail to read msg from queue %d", queue->id);
                         *status = err;
@@ -750,7 +750,7 @@ int pmu_wait_message_cond(struct nvgpu_pmu *pmu, u32 timeout_ms,
 
                 nvgpu_usleep_range(delay, delay * 2U);
                 delay = min_t(u32, delay << 1, GR_IDLE_CHECK_MAX);
-        } while (!nvgpu_timeout_expired(&timeout));
+        } while (nvgpu_timeout_expired(&timeout) == 0);
 
         return -ETIMEDOUT;
 }
@@ -887,7 +887,7 @@ int nvgpu_pmu_rpc_execute(struct nvgpu_pmu *pmu, struct nv_pmu_rpc_header *rpc,
         if (caller_cb == NULL) {
                 rpc_payload = nvgpu_kzalloc(g,
                         sizeof(struct rpc_handler_payload) + size_rpc);
-                if (!rpc_payload) {
+                if (rpc_payload == NULL) {
                         status = ENOMEM;
                         goto exit;
                 }
@@ -907,7 +907,7 @@ int nvgpu_pmu_rpc_execute(struct nvgpu_pmu *pmu, struct nv_pmu_rpc_header *rpc,
                 }
                 rpc_payload = nvgpu_kzalloc(g,
                         sizeof(struct rpc_handler_payload));
-                if (!rpc_payload) {
+                if (rpc_payload == NULL) {
                         status = ENOMEM;
                         goto exit;
                 }
diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_perfmon.c b/drivers/gpu/nvgpu/common/pmu/pmu_perfmon.c
index a99e86ce..12ab4422 100644
--- a/drivers/gpu/nvgpu/common/pmu/pmu_perfmon.c
+++ b/drivers/gpu/nvgpu/common/pmu/pmu_perfmon.c
@@ -51,7 +51,7 @@ static u8 get_perfmon_id(struct nvgpu_pmu *pmu)
         default:
                 unit_id = PMU_UNIT_INVALID;
                 nvgpu_err(g, "no support for %x", ver);
-                WARN_ON(1);
+                WARN_ON(true);
         }
 
         return unit_id;
@@ -75,11 +75,11 @@ int nvgpu_pmu_init_perfmon(struct nvgpu_pmu *pmu)
 
         g->ops.pmu.pmu_init_perfmon_counter(g);
 
-        if (!pmu->sample_buffer) {
+        if (pmu->sample_buffer == 0U) {
                 pmu->sample_buffer = nvgpu_alloc(&pmu->dmem,
                                                   2U * sizeof(u16));
         }
-        if (!pmu->sample_buffer) {
+        if (pmu->sample_buffer == 0U) {
                 nvgpu_err(g, "failed to allocate perfmon sample buffer");
                 return -ENOMEM;
         }
@@ -240,7 +240,7 @@ int nvgpu_pmu_load_update(struct gk20a *g)
 void nvgpu_pmu_get_load_counters(struct gk20a *g, u32 *busy_cycles,
                                  u32 *total_cycles)
 {
-        if (!g->power_on || gk20a_busy(g)) {
+        if (!g->power_on || gk20a_busy(g) != 0) {
                 *busy_cycles = 0;
                 *total_cycles = 0;
                 return;
@@ -254,7 +254,7 @@ void nvgpu_pmu_get_load_counters(struct gk20a *g, u32 *busy_cycles,
 
 void nvgpu_pmu_reset_load_counters(struct gk20a *g)
 {
-        if (!g->power_on || gk20a_busy(g)) {
+        if (!g->power_on || gk20a_busy(g) != 0) {
                 return;
         }
 
diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_pg.c b/drivers/gpu/nvgpu/common/pmu/pmu_pg.c
index 0758279d..d2615b1a 100644
--- a/drivers/gpu/nvgpu/common/pmu/pmu_pg.c
+++ b/drivers/gpu/nvgpu/common/pmu/pmu_pg.c
@@ -89,9 +89,9 @@ static void pmu_handle_pg_elpg_msg(struct gk20a *g, struct pmu_msg *msg,
                 }
 
                 if (pmu->pmu_state == PMU_STATE_ELPG_BOOTING) {
-                        if (g->ops.pmu.pmu_pg_engines_feature_list &&
+                        if (g->ops.pmu.pmu_pg_engines_feature_list != NULL &&
                                 g->ops.pmu.pmu_pg_engines_feature_list(g,
-                                PMU_PG_ELPG_ENGINE_ID_GRAPHICS) !=
+                                        PMU_PG_ELPG_ENGINE_ID_GRAPHICS) !=
                                 NVGPU_PMU_GR_FEATURE_MASK_POWER_GATING) {
                                 pmu->initialized = true;
                                 nvgpu_pmu_state_change(g, PMU_STATE_STARTED,
@@ -117,9 +117,9 @@ int nvgpu_pmu_pg_global_enable(struct gk20a *g, u32 enable_pg)
         u32 status = 0;
 
         if (enable_pg == true) {
-                if (g->ops.pmu.pmu_pg_engines_feature_list &&
+                if (g->ops.pmu.pmu_pg_engines_feature_list != NULL &&
                         g->ops.pmu.pmu_pg_engines_feature_list(g,
-                        PMU_PG_ELPG_ENGINE_ID_GRAPHICS) !=
+                                PMU_PG_ELPG_ENGINE_ID_GRAPHICS) !=
                         NVGPU_PMU_GR_FEATURE_MASK_POWER_GATING) {
                         if (g->ops.pmu.pmu_lpwr_enable_pg) {
                                 status = g->ops.pmu.pmu_lpwr_enable_pg(g,
@@ -129,9 +129,9 @@ int nvgpu_pmu_pg_global_enable(struct gk20a *g, u32 enable_pg)
                         status = nvgpu_pmu_enable_elpg(g);
                 }
         } else if (enable_pg == false) {
-                if (g->ops.pmu.pmu_pg_engines_feature_list &&
+                if (g->ops.pmu.pmu_pg_engines_feature_list != NULL &&
                         g->ops.pmu.pmu_pg_engines_feature_list(g,
-                        PMU_PG_ELPG_ENGINE_ID_GRAPHICS) !=
+                                PMU_PG_ELPG_ENGINE_ID_GRAPHICS) !=
                         NVGPU_PMU_GR_FEATURE_MASK_POWER_GATING) {
                         if (g->ops.pmu.pmu_lpwr_disable_pg) {
                                 status = g->ops.pmu.pmu_lpwr_disable_pg(g,
@@ -207,7 +207,7 @@ int nvgpu_pmu_enable_elpg(struct gk20a *g)
                 nvgpu_warn(g,
                         "%s(): possible elpg refcnt mismatch. elpg refcnt=%d",
                         __func__, pmu->elpg_refcnt);
-                WARN_ON(1);
+                WARN_ON(true);
         }
 
         /* do NOT enable elpg until golden ctx is created,
@@ -273,7 +273,7 @@ int nvgpu_pmu_disable_elpg(struct gk20a *g)
                 nvgpu_warn(g,
                         "%s(): possible elpg refcnt mismatch. elpg refcnt=%d",
                         __func__, pmu->elpg_refcnt);
-                WARN_ON(1);
+                WARN_ON(true);
                 ret = 0;
                 goto exit_unlock;
         }
@@ -481,7 +481,8 @@ int nvgpu_pmu_init_powergating(struct gk20a *g)
                         pg_engine_id++) {
 
                 if (BIT(pg_engine_id) & pg_engine_id_list) {
-                        if (pmu && pmu->pmu_state == PMU_STATE_INIT_RECEIVED) {
+                        if (pmu != NULL &&
+                            pmu->pmu_state == PMU_STATE_INIT_RECEIVED) {
                                 nvgpu_pmu_state_change(g,
                                         PMU_STATE_ELPG_BOOTING, false);
                         }
@@ -636,9 +637,9 @@ static void ap_callback_init_and_enable_ctrl(
                 void *param, u32 seq_desc, u32 status)
 {
         /* Define p_ap (i.e pointer to pmu_ap structure) */
-        WARN_ON(!msg);
+        WARN_ON(msg == NULL);
 
-        if (!status) {
+        if (status == 0U) {
                 switch (msg->msg.pg.ap_msg.cmn.msg_id) {
                 case PMU_AP_MSG_ID_INIT_ACK:
                         nvgpu_pmu_dbg(g, "reply PMU_AP_CMD_ID_INIT");