gpu: nvgpu: invoke calls to methods in pmu_gk20a.h via HAL

In nvgpu repository, we have multiple accesses to methods in
pmu_gk20a.h which have register accesses. Instead of directly invoking
these methods, these are now called via HALs. Some common methods such
as pmu_wait_message_cond which donot have any register accesses
are moved to pmu_ipc.c and the method declarations are moved
to pmu.h. Also, changed gm20b_pmu_dbg to
nvgpu_dbg_pmu all across the code base. This would remove all
indirect dependencies via gk20a.h into pmu_gk20a.h. As a result
pmu_gk20a.h is now removed from gk20a.h

JIRA-597

Change-Id: Id54b2684ca39362fda7626238c3116cd49e92080
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1804283
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

5 files changed, 14 insertions, 14 deletions

diff --git a/drivers/gpu/nvgpu/common/pmu/pmu.c b/drivers/gpu/nvgpu/common/pmu/pmu.c
index 86e56d9e..0395e463 100644
--- a/drivers/gpu/nvgpu/common/pmu/pmu.c
+++ b/drivers/gpu/nvgpu/common/pmu/pmu.c
@@ -81,7 +81,7 @@ static int pmu_enable(struct nvgpu_pmu *pmu, bool enable)
 
         if (!enable) {
                 if (!g->ops.pmu.is_engine_in_reset(g)) {
-                        pmu_enable_irq(pmu, false);
+                        g->ops.pmu.pmu_enable_irq(pmu, false);
                         pmu_enable_hw(pmu, false);
                 }
         } else {
@@ -95,7 +95,7 @@ static int pmu_enable(struct nvgpu_pmu *pmu, bool enable)
                         goto exit;
                 }
 
-                pmu_enable_irq(pmu, true);
+                g->ops.pmu.pmu_enable_irq(pmu, true);
         }
 
 exit:
@@ -412,7 +412,7 @@ static void pmu_setup_hw_enable_elpg(struct gk20a *g)
         if (nvgpu_is_enabled(g, NVGPU_PMU_ZBC_SAVE)) {
                 /* Save zbc table after PMU is initialized. */
                 pmu->zbc_ready = true;
-                gk20a_pmu_save_zbc(g, 0xf);
+                g->ops.gr.pmu_save_zbc(g, 0xf);
         }
 
         if (g->elpg_enabled) {
diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_debug.c b/drivers/gpu/nvgpu/common/pmu/pmu_debug.c
index 6ad82ca8..68a39432 100644
--- a/drivers/gpu/nvgpu/common/pmu/pmu_debug.c
+++ b/drivers/gpu/nvgpu/common/pmu/pmu_debug.c
@@ -39,7 +39,7 @@ void nvgpu_pmu_dump_elpg_stats(struct nvgpu_pmu *pmu)
                 pmu->stat_dmem_offset[PMU_PG_ELPG_ENGINE_ID_GRAPHICS],
                 sizeof(struct pmu_pg_stats_v2));
 
-        gk20a_pmu_dump_elpg_stats(pmu);
+        g->ops.pmu.pmu_dump_elpg_stats(pmu);
 }
 
 void nvgpu_pmu_dump_falcon_stats(struct nvgpu_pmu *pmu)
@@ -47,7 +47,7 @@ void nvgpu_pmu_dump_falcon_stats(struct nvgpu_pmu *pmu)
         struct gk20a *g = pmu->g;
 
         nvgpu_flcn_dump_stats(pmu->flcn);
-        gk20a_pmu_dump_falcon_stats(pmu);
+        g->ops.pmu.pmu_dump_falcon_stats(pmu);
 
         nvgpu_err(g, "pmu state: %d", pmu->pmu_state);
         nvgpu_err(g, "elpg state: %d", pmu->elpg_stat);
diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_ipc.c b/drivers/gpu/nvgpu/common/pmu/pmu_ipc.c
index 843a4551..9fe999ae 100644
--- a/drivers/gpu/nvgpu/common/pmu/pmu_ipc.c
+++ b/drivers/gpu/nvgpu/common/pmu/pmu_ipc.c
@@ -744,8 +744,8 @@ int pmu_wait_message_cond(struct nvgpu_pmu *pmu, u32 timeout_ms,
                         return 0;
                 }
 
-                if (gk20a_pmu_is_interrupted(pmu)) {
-                        gk20a_pmu_isr(g);
+                if (g->ops.pmu.pmu_is_interrupted(pmu)) {
+                        g->ops.pmu.pmu_isr(g);
                 }
 
                 nvgpu_usleep_range(delay, delay * 2U);
diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_perfmon.c b/drivers/gpu/nvgpu/common/pmu/pmu_perfmon.c
index 5d736591..a99e86ce 100644
--- a/drivers/gpu/nvgpu/common/pmu/pmu_perfmon.c
+++ b/drivers/gpu/nvgpu/common/pmu/pmu_perfmon.c
@@ -73,7 +73,7 @@ int nvgpu_pmu_init_perfmon(struct nvgpu_pmu *pmu)
 
         pmu->perfmon_ready = 0;
 
-        gk20a_pmu_init_perfmon_counter(g);
+        g->ops.pmu.pmu_init_perfmon_counter(g);
 
         if (!pmu->sample_buffer) {
                 pmu->sample_buffer = nvgpu_alloc(&pmu->dmem,
@@ -246,8 +246,8 @@ void nvgpu_pmu_get_load_counters(struct gk20a *g, u32 *busy_cycles,
                 return;
         }
 
-        *busy_cycles = gk20a_pmu_read_idle_counter(g, 1);
-        *total_cycles = gk20a_pmu_read_idle_counter(g, 2);
+        *busy_cycles = g->ops.pmu.pmu_read_idle_counter(g, 1);
+        *total_cycles = g->ops.pmu.pmu_read_idle_counter(g, 2);
 
         gk20a_idle(g);
 }
@@ -258,8 +258,8 @@ void nvgpu_pmu_reset_load_counters(struct gk20a *g)
                 return;
         }
 
-        gk20a_pmu_reset_idle_counter(g, 2);
-        gk20a_pmu_reset_idle_counter(g, 1);
+        g->ops.pmu.pmu_reset_idle_counter(g, 2);
+        g->ops.pmu.pmu_reset_idle_counter(g, 1);
 
         gk20a_idle(g);
 }
@@ -316,7 +316,7 @@ int nvgpu_pmu_init_perfmon_rpc(struct nvgpu_pmu *pmu)
         memset(&rpc, 0, sizeof(struct nv_pmu_rpc_struct_perfmon_init));
         pmu->perfmon_ready = 0;
 
-        gk20a_pmu_init_perfmon_counter(g);
+        g->ops.pmu.pmu_init_perfmon_counter(g);
 
         /* microseconds interval between pmu polls perf counters */
         rpc.sample_periodus = 16700;
diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_pg.c b/drivers/gpu/nvgpu/common/pmu/pmu_pg.c
index 76ed0621..0758279d 100644
--- a/drivers/gpu/nvgpu/common/pmu/pmu_pg.c
+++ b/drivers/gpu/nvgpu/common/pmu/pmu_pg.c
@@ -394,7 +394,7 @@ static int pmu_pg_init_send(struct gk20a *g, u32 pg_engine_id)
 
         nvgpu_log_fn(g, " ");
 
-        gk20a_pmu_pg_idle_counter_config(g, pg_engine_id);
+        g->ops.pmu.pmu_pg_idle_counter_config(g, pg_engine_id);
 
         if (g->ops.pmu.pmu_pg_init_param) {
                 g->ops.pmu.pmu_pg_init_param(g, pg_engine_id);