gpu: nvgpu: common: Fix MISRA 15.6 violations

This fixes errors due to single statement loop bodies
 without braces, which is part of Rule 15.6 of MISRA.
 This patch covers in gpu/nvgpu/common/

JIRA NVGPU-989

Change-Id: Ic6a98a1cd04e4524dabf650e2f6e73c6b5a1db9d
Signed-off-by: Srirangan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1786207
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Adeel Raza <araza@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

3 files changed, 13 insertions, 7 deletions

diff --git a/drivers/gpu/nvgpu/common/pmu/pmu.c b/drivers/gpu/nvgpu/common/pmu/pmu.c
index 327f67d3..2dcadb48 100644
--- a/drivers/gpu/nvgpu/common/pmu/pmu.c
+++ b/drivers/gpu/nvgpu/common/pmu/pmu.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -358,8 +358,9 @@ int nvgpu_pmu_process_init_msg(struct nvgpu_pmu *pmu,
                 }
         }
 
-        for (i = 0; i < PMU_QUEUE_COUNT; i++)
+        for (i = 0; i < PMU_QUEUE_COUNT; i++) {
                 nvgpu_pmu_queue_init(pmu, i, init);
+        }
 
         if (!nvgpu_alloc_initialized(&pmu->dmem)) {
                 /* Align start and end addresses */
@@ -480,8 +481,9 @@ static int nvgpu_pg_init_task(void *arg)
 
         }
 
-        while (!nvgpu_thread_should_stop(&pg_init->state_task))
+        while (!nvgpu_thread_should_stop(&pg_init->state_task)) {
                 nvgpu_usleep_range(5000, 5100);
+        }
 
         nvgpu_log_fn(g, "thread exit");
 
diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_fw.c b/drivers/gpu/nvgpu/common/pmu/pmu_fw.c
index 53eae49a..fc328401 100644
--- a/drivers/gpu/nvgpu/common/pmu/pmu_fw.c
+++ b/drivers/gpu/nvgpu/common/pmu/pmu_fw.c
@@ -881,8 +881,9 @@ static void get_pmu_init_msg_pmu_queue_params_v4(
         queue->index    = init->queue_index[tmp_id];
         queue->size = init->queue_size[tmp_id];
         if (tmp_id != 0) {
-                for (i = 0 ; i < tmp_id; i++)
+                for (i = 0 ; i < tmp_id; i++) {
                         current_ptr += init->queue_size[i];
+                }
         }
         queue->offset   = init->queue_offset + current_ptr;
 }
@@ -908,8 +909,9 @@ static void get_pmu_init_msg_pmu_queue_params_v5(
         queue->index    = init->queue_index[tmp_id];
         queue->size = init->queue_size[tmp_id];
         if (tmp_id != 0) {
-                for (i = 0 ; i < tmp_id; i++)
+                for (i = 0 ; i < tmp_id; i++) {
                         current_ptr += init->queue_size[i];
+                }
         }
         queue->offset   = init->queue_offset + current_ptr;
 }
@@ -935,8 +937,9 @@ static void get_pmu_init_msg_pmu_queue_params_v3(
         queue->index    = init->queue_index[tmp_id];
         queue->size = init->queue_size[tmp_id];
         if (tmp_id != 0) {
-                for (i = 0 ; i < tmp_id; i++)
+                for (i = 0 ; i < tmp_id; i++) {
                         current_ptr += init->queue_size[i];
+                }
         }
         queue->offset   = init->queue_offset + current_ptr;
 }
diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_ipc.c b/drivers/gpu/nvgpu/common/pmu/pmu_ipc.c
index f34e942d..cb7c10a3 100644
--- a/drivers/gpu/nvgpu/common/pmu/pmu_ipc.c
+++ b/drivers/gpu/nvgpu/common/pmu/pmu_ipc.c
@@ -39,8 +39,9 @@ void nvgpu_pmu_seq_init(struct nvgpu_pmu *pmu)
         memset(pmu->pmu_seq_tbl, 0,
                 sizeof(pmu->pmu_seq_tbl));
 
-        for (i = 0; i < PMU_MAX_NUM_SEQUENCES; i++)
+        for (i = 0; i < PMU_MAX_NUM_SEQUENCES; i++) {
                 pmu->seq[i].id = i;
+        }
 }
 
 static int pmu_seq_acquire(struct nvgpu_pmu *pmu,