gpu: nvgpu: pmu: Fix pmu_state state update

- Commit c61e21c868246faf7a9ffc812590941fc362af17 fixed race codition in PMU
  state transition.
- The race condition is such that PMU response(intr callback for messages) can
  run faster than kthread posting commands to PMU and thus PMU message callback
  may skip important pmu state change.
- Commit c61e21c868246faf7a9ffc812590941fc362af17 introduced a fix where PMU
  state change was only updated from callback while other places can only update
  pmu_state variable
- However, this commit introduced a regression as follows:
  - When PMU state is PMU_STATE_INIT_RECEIVED, we loop over every engine
    supported by GPU --> If state = PMU_STATE_INIT_RECEIVED, change the state
    to PMU_STATE_ELPG_BOOTING and init ELPG else If state != PMU_STATE_INIT_RECEIVED
    throw an error saying "PMU INIT not received"
  - Now, if GPU supports multiple engines, first engine will check that
    pmu_state is PMU_STATE_INIT_RECEIVED and change it to PMU_STATE_ELPG_BOOTING
    However, from second engine onwards, since state is already changed to
    PMU_STATE_ELPG_BOOTING, all engines except first engine start throwing
    error "PMU INIT not received"
- This patch fixes the issue by changing pmu state from
  PMU_STATE_INIT_RECEIVED to PMU_STATE_ELPG_BOOTING only once.

Bug 200372838
JIRA EVLR-2164

Change-Id: Ic8c954d14acb1d6ec3adcbc4bcf4d4745542d9f0
Signed-off-by: Deepak Bhosale <dbhosale@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1769814
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-by: Aparna Das <aparnad@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 5 insertions, 7 deletions

diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_pg.c b/drivers/gpu/nvgpu/common/pmu/pmu_pg.c
index 2d0fc499..30bf9008 100644
--- a/drivers/gpu/nvgpu/common/pmu/pmu_pg.c
+++ b/drivers/gpu/nvgpu/common/pmu/pmu_pg.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -374,12 +374,6 @@ static int pmu_pg_init_send(struct gk20a *g, u32 pg_engine_id)
 
         nvgpu_log_fn(g, " ");
 
-        if (pmu->pmu_state == PMU_STATE_INIT_RECEIVED)
-                nvgpu_pmu_state_change(g,
-                                PMU_STATE_ELPG_BOOTING, false);
-        else
-                nvgpu_err(g, "PMU INIT not received\n");
-
         gk20a_pmu_pg_idle_counter_config(g, pg_engine_id);
 
         if (g->ops.pmu.pmu_pg_init_param)
@@ -446,6 +440,7 @@ int nvgpu_pmu_init_powergating(struct gk20a *g)
 {
         u32 pg_engine_id;
         u32 pg_engine_id_list = 0;
+        struct nvgpu_pmu *pmu = &g->pmu;
 
         nvgpu_log_fn(g, " ");
 
@@ -459,6 +454,9 @@ int nvgpu_pmu_init_powergating(struct gk20a *g)
                         pg_engine_id++) {
 
                 if (BIT(pg_engine_id) & pg_engine_id_list) {
+                        if (pmu && pmu->pmu_state == PMU_STATE_INIT_RECEIVED)
+                                nvgpu_pmu_state_change(g,
+                                        PMU_STATE_ELPG_BOOTING, false);
                         pmu_pg_init_send(g, pg_engine_id);
                 }
         }