gpu: nvgpu: gv11b: Correct PMU PG enabled masks.

PMU ucode records supported feature list for a
particular chip as support mask sent
via PMU_PG_PARAM_CMD_GR_INIT_PARAM.

It then enables selective feature list through
enable mask sent via
PMU_PG_PARAM_CMD_SUB_FEATURE_MASK_UPDATE cmd.

Right now only ELPG state machine mask was enabled.
Only ELPG state machine was getting executed
but other crucial steps in ELPG entry/exit sequence
were getting skipped.

Bug 200392620.
Bug 200296076.

Change-Id: I5e1800980990c146c731537290cb7d4c07e937c3
Signed-off-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1665767
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 3 insertions, 3 deletions

diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_pg.c b/drivers/gpu/nvgpu/common/pmu/pmu_pg.c
index bf39ce19..2d0fc499 100644
--- a/drivers/gpu/nvgpu/common/pmu/pmu_pg.c
+++ b/drivers/gpu/nvgpu/common/pmu/pmu_pg.c
@@ -89,7 +89,7 @@ static void pmu_handle_pg_elpg_msg(struct gk20a *g, struct pmu_msg *msg,
                         if (g->ops.pmu.pmu_pg_engines_feature_list &&
                                 g->ops.pmu.pmu_pg_engines_feature_list(g,
                                 PMU_PG_ELPG_ENGINE_ID_GRAPHICS) !=
-                                PMU_PG_FEATURE_GR_POWER_GATING_ENABLED) {
+                                NVGPU_PMU_GR_FEATURE_MASK_POWER_GATING) {
                                 pmu->initialized = true;
                                 nvgpu_pmu_state_change(g, PMU_STATE_STARTED,
                                         true);
@@ -116,7 +116,7 @@ int nvgpu_pmu_pg_global_enable(struct gk20a *g, u32 enable_pg)
                 if (g->ops.pmu.pmu_pg_engines_feature_list &&
                         g->ops.pmu.pmu_pg_engines_feature_list(g,
                         PMU_PG_ELPG_ENGINE_ID_GRAPHICS) !=
-                        PMU_PG_FEATURE_GR_POWER_GATING_ENABLED) {
+                        NVGPU_PMU_GR_FEATURE_MASK_POWER_GATING) {
                         if (g->ops.pmu.pmu_lpwr_enable_pg)
                                 status = g->ops.pmu.pmu_lpwr_enable_pg(g,
                                                 true);
@@ -126,7 +126,7 @@ int nvgpu_pmu_pg_global_enable(struct gk20a *g, u32 enable_pg)
                 if (g->ops.pmu.pmu_pg_engines_feature_list &&
                         g->ops.pmu.pmu_pg_engines_feature_list(g,
                         PMU_PG_ELPG_ENGINE_ID_GRAPHICS) !=
-                        PMU_PG_FEATURE_GR_POWER_GATING_ENABLED) {
+                        NVGPU_PMU_GR_FEATURE_MASK_POWER_GATING) {
                         if (g->ops.pmu.pmu_lpwr_disable_pg)
                                 status = g->ops.pmu.pmu_lpwr_disable_pg(g,
                                                 true);