diff options
author | Deepak Goyal <dgoyal@nvidia.com> | 2017-06-15 11:07:36 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-06-19 11:35:16 -0400 |
commit | 077d4c6da3f27c7cb2096fed26eb8e8c77fca77f (patch) | |
tree | b60b2d6b872e689db66300df2ba05a24984c8bf7 /drivers/gpu/nvgpu/common/pmu/pmu_pg.c | |
parent | e6edb10656c86bbc8918c63ae99be25c2e343a99 (diff) |
gpu : nvgpu: Update sub-feature mask for ELPG.
This patch also adds new interface for GR INIT PARAM cmd
and adds new pmu command to update sub-feature mask for ELPG.
JIRA GPUT19X-20.
Change-Id: Id3b3b65882c714f80a05de5660895258b26a08bd
Signed-off-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-on: http://git-master/r/1503141
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/common/pmu/pmu_pg.c')
-rw-r--r-- | drivers/gpu/nvgpu/common/pmu/pmu_pg.c | 15 |
1 files changed, 9 insertions, 6 deletions
diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_pg.c b/drivers/gpu/nvgpu/common/pmu/pmu_pg.c index 046f4d59..47ac8b64 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu_pg.c +++ b/drivers/gpu/nvgpu/common/pmu/pmu_pg.c | |||
@@ -60,19 +60,19 @@ static void pmu_handle_pg_elpg_msg(struct gk20a *g, struct pmu_msg *msg, | |||
60 | case PMU_PG_ELPG_MSG_ALLOW_ACK: | 60 | case PMU_PG_ELPG_MSG_ALLOW_ACK: |
61 | nvgpu_pmu_dbg(g, "ALLOW is ack from PMU, eng - %d", | 61 | nvgpu_pmu_dbg(g, "ALLOW is ack from PMU, eng - %d", |
62 | elpg_msg->engine_id); | 62 | elpg_msg->engine_id); |
63 | if (elpg_msg->engine_id == PMU_PG_ELPG_ENGINE_ID_GRAPHICS) | 63 | if (elpg_msg->engine_id == PMU_PG_ELPG_ENGINE_ID_MS) |
64 | pmu->elpg_stat = PMU_ELPG_STAT_ON; | ||
65 | else if (elpg_msg->engine_id == PMU_PG_ELPG_ENGINE_ID_MS) | ||
66 | pmu->mscg_transition_state = PMU_ELPG_STAT_ON; | 64 | pmu->mscg_transition_state = PMU_ELPG_STAT_ON; |
65 | else | ||
66 | pmu->elpg_stat = PMU_ELPG_STAT_ON; | ||
67 | break; | 67 | break; |
68 | case PMU_PG_ELPG_MSG_DISALLOW_ACK: | 68 | case PMU_PG_ELPG_MSG_DISALLOW_ACK: |
69 | nvgpu_pmu_dbg(g, "DISALLOW is ack from PMU, eng - %d", | 69 | nvgpu_pmu_dbg(g, "DISALLOW is ack from PMU, eng - %d", |
70 | elpg_msg->engine_id); | 70 | elpg_msg->engine_id); |
71 | 71 | ||
72 | if (elpg_msg->engine_id == PMU_PG_ELPG_ENGINE_ID_GRAPHICS) | 72 | if (elpg_msg->engine_id == PMU_PG_ELPG_ENGINE_ID_MS) |
73 | pmu->elpg_stat = PMU_ELPG_STAT_OFF; | ||
74 | else if (elpg_msg->engine_id == PMU_PG_ELPG_ENGINE_ID_MS) | ||
75 | pmu->mscg_transition_state = PMU_ELPG_STAT_OFF; | 73 | pmu->mscg_transition_state = PMU_ELPG_STAT_OFF; |
74 | else | ||
75 | pmu->elpg_stat = PMU_ELPG_STAT_OFF; | ||
76 | 76 | ||
77 | if (pmu->pmu_state == PMU_STATE_ELPG_BOOTING) { | 77 | if (pmu->pmu_state == PMU_STATE_ELPG_BOOTING) { |
78 | if (g->ops.pmu.pmu_pg_engines_feature_list && | 78 | if (g->ops.pmu.pmu_pg_engines_feature_list && |
@@ -412,6 +412,9 @@ static int pmu_pg_init_send(struct gk20a *g, u32 pg_engine_id) | |||
412 | gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, | 412 | gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, |
413 | pmu_handle_pg_elpg_msg, pmu, &seq, ~0); | 413 | pmu_handle_pg_elpg_msg, pmu, &seq, ~0); |
414 | 414 | ||
415 | if (g->ops.pmu.pmu_pg_set_sub_feature_mask) | ||
416 | g->ops.pmu.pmu_pg_set_sub_feature_mask(g, pg_engine_id); | ||
417 | |||
415 | return 0; | 418 | return 0; |
416 | } | 419 | } |
417 | 420 | ||