diff options
author | Mahantesh Kumbar <mkumbar@nvidia.com> | 2017-07-04 01:55:00 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-07-05 03:39:21 -0400 |
commit | e808d345f11885453fc65862ec4e3dd4a375ff6d (patch) | |
tree | ccc3bb1ade5ff991ca1805084b76f154ca9736ee /drivers/gpu/nvgpu/common/pmu/pmu_perfmon.c | |
parent | 2cf964d175abc0f3eae9ed0e01e6eeed5cd6b4da (diff) |
gpu: nvgpu: rename gk20a_pmu_cmd_post()
- rename gk20a_pmu_cmd_post() to nvgpu_pmu_cmd_post()
- replaced gk20a_pmu_cmd_post() with nvgpu_pmu_cmd_post()
wherever called.
JIRA NVGPU-93
Change-Id: I7ca43170646bab1657a4b4cf125d9f94d589b0eb
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master/r/1512904
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/common/pmu/pmu_perfmon.c')
-rw-r--r-- | drivers/gpu/nvgpu/common/pmu/pmu_perfmon.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_perfmon.c b/drivers/gpu/nvgpu/common/pmu/pmu_perfmon.c index 750906ce..f87bd175 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu_perfmon.c +++ b/drivers/gpu/nvgpu/common/pmu/pmu_perfmon.c | |||
@@ -112,7 +112,7 @@ int nvgpu_pmu_init_perfmon(struct nvgpu_pmu *pmu) | |||
112 | payload.in.offset = pv->get_perfmon_cmd_init_offsetofvar(COUNTER_ALLOC); | 112 | payload.in.offset = pv->get_perfmon_cmd_init_offsetofvar(COUNTER_ALLOC); |
113 | 113 | ||
114 | nvgpu_pmu_dbg(g, "cmd post PMU_PERFMON_CMD_ID_INIT"); | 114 | nvgpu_pmu_dbg(g, "cmd post PMU_PERFMON_CMD_ID_INIT"); |
115 | gk20a_pmu_cmd_post(g, &cmd, NULL, &payload, PMU_COMMAND_QUEUE_LPQ, | 115 | nvgpu_pmu_cmd_post(g, &cmd, NULL, &payload, PMU_COMMAND_QUEUE_LPQ, |
116 | NULL, NULL, &seq, ~0); | 116 | NULL, NULL, &seq, ~0); |
117 | 117 | ||
118 | return 0; | 118 | return 0; |
@@ -160,7 +160,7 @@ int nvgpu_pmu_perfmon_start_sampling(struct nvgpu_pmu *pmu) | |||
160 | pv->get_perfmon_cmd_start_offsetofvar(COUNTER_ALLOC); | 160 | pv->get_perfmon_cmd_start_offsetofvar(COUNTER_ALLOC); |
161 | 161 | ||
162 | nvgpu_pmu_dbg(g, "cmd post PMU_PERFMON_CMD_ID_START"); | 162 | nvgpu_pmu_dbg(g, "cmd post PMU_PERFMON_CMD_ID_START"); |
163 | gk20a_pmu_cmd_post(g, &cmd, NULL, &payload, PMU_COMMAND_QUEUE_LPQ, | 163 | nvgpu_pmu_cmd_post(g, &cmd, NULL, &payload, PMU_COMMAND_QUEUE_LPQ, |
164 | NULL, NULL, &seq, ~0); | 164 | NULL, NULL, &seq, ~0); |
165 | 165 | ||
166 | return 0; | 166 | return 0; |
@@ -183,7 +183,7 @@ int nvgpu_pmu_perfmon_stop_sampling(struct nvgpu_pmu *pmu) | |||
183 | cmd.cmd.perfmon.stop.cmd_type = PMU_PERFMON_CMD_ID_STOP; | 183 | cmd.cmd.perfmon.stop.cmd_type = PMU_PERFMON_CMD_ID_STOP; |
184 | 184 | ||
185 | nvgpu_pmu_dbg(g, "cmd post PMU_PERFMON_CMD_ID_STOP"); | 185 | nvgpu_pmu_dbg(g, "cmd post PMU_PERFMON_CMD_ID_STOP"); |
186 | gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_LPQ, | 186 | nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_LPQ, |
187 | NULL, NULL, &seq, ~0); | 187 | NULL, NULL, &seq, ~0); |
188 | return 0; | 188 | return 0; |
189 | } | 189 | } |