gpu: nvgpu: invoke calls to methods in pmu_gk20a.h via HAL

In nvgpu repository, we have multiple accesses to methods in
pmu_gk20a.h which have register accesses. Instead of directly invoking
these methods, these are now called via HALs. Some common methods such
as pmu_wait_message_cond which donot have any register accesses
are moved to pmu_ipc.c and the method declarations are moved
to pmu.h. Also, changed gm20b_pmu_dbg to
nvgpu_dbg_pmu all across the code base. This would remove all
indirect dependencies via gk20a.h into pmu_gk20a.h. As a result
pmu_gk20a.h is now removed from gk20a.h

JIRA-597

Change-Id: Id54b2684ca39362fda7626238c3116cd49e92080
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1804283
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 6 insertions, 6 deletions

diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_perfmon.c b/drivers/gpu/nvgpu/common/pmu/pmu_perfmon.c
index 5d736591..a99e86ce 100644
--- a/drivers/gpu/nvgpu/common/pmu/pmu_perfmon.c
+++ b/drivers/gpu/nvgpu/common/pmu/pmu_perfmon.c
@@ -73,7 +73,7 @@ int nvgpu_pmu_init_perfmon(struct nvgpu_pmu *pmu)
 
         pmu->perfmon_ready = 0;
 
-        gk20a_pmu_init_perfmon_counter(g);
+        g->ops.pmu.pmu_init_perfmon_counter(g);
 
         if (!pmu->sample_buffer) {
                 pmu->sample_buffer = nvgpu_alloc(&pmu->dmem,
@@ -246,8 +246,8 @@ void nvgpu_pmu_get_load_counters(struct gk20a *g, u32 *busy_cycles,
                 return;
         }
 
-        *busy_cycles = gk20a_pmu_read_idle_counter(g, 1);
-        *total_cycles = gk20a_pmu_read_idle_counter(g, 2);
+        *busy_cycles = g->ops.pmu.pmu_read_idle_counter(g, 1);
+        *total_cycles = g->ops.pmu.pmu_read_idle_counter(g, 2);
 
         gk20a_idle(g);
 }
@@ -258,8 +258,8 @@ void nvgpu_pmu_reset_load_counters(struct gk20a *g)
                 return;
         }
 
-        gk20a_pmu_reset_idle_counter(g, 2);
-        gk20a_pmu_reset_idle_counter(g, 1);
+        g->ops.pmu.pmu_reset_idle_counter(g, 2);
+        g->ops.pmu.pmu_reset_idle_counter(g, 1);
 
         gk20a_idle(g);
 }
@@ -316,7 +316,7 @@ int nvgpu_pmu_init_perfmon_rpc(struct nvgpu_pmu *pmu)
         memset(&rpc, 0, sizeof(struct nv_pmu_rpc_struct_perfmon_init));
         pmu->perfmon_ready = 0;
 
-        gk20a_pmu_init_perfmon_counter(g);
+        g->ops.pmu.pmu_init_perfmon_counter(g);
 
         /* microseconds interval between pmu polls perf counters */
         rpc.sample_periodus = 16700;