gpu: nvgpu: gv100: BOOTSTRAP_GR_FALCONS using RPC

- Created nv_pmu_rpc_struct_acr_bootstrap_gr_falcons struct
- gv100_load_falcon_ucode() function to bootstrap GR
flacons using RPC, wait for INIT_WPR_REGION before
creating & executing BOOTSTRAP_GR_FALCONS RPC.
- Added code to handle BOOTSTRAP_GR_FALCONS ack in
RPC handler

Change-Id: If70dc75bb2789970382853fb001d970a346b2915
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1613316
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 5 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_ipc.c b/drivers/gpu/nvgpu/common/pmu/pmu_ipc.c
index 77acbafc..72337a1d 100644
--- a/drivers/gpu/nvgpu/common/pmu/pmu_ipc.c
+++ b/drivers/gpu/nvgpu/common/pmu/pmu_ipc.c
@@ -1000,6 +1000,11 @@ static void pmu_rpc_handler(struct gk20a *g, struct pmu_msg *msg,
                                 "reply NV_PMU_RPC_ID_ACR_INIT_WPR_REGION");
                         g->pmu_lsf_pmu_wpr_init_done = 1;
                         break;
+                case NV_PMU_RPC_ID_ACR_BOOTSTRAP_GR_FALCONS:
+                        nvgpu_pmu_dbg(g,
+                                "reply NV_PMU_RPC_ID_ACR_BOOTSTRAP_GR_FALCONS");
+                        g->pmu_lsf_loaded_falcon_id = 1;
+                        break;
                 }
                 break;
         case PMU_UNIT_PERFMON_T18X: