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| author | Philemon Gardet <pgardet@nvidia.com> | 2018-07-20 23:37:54 -0400 |
|---|---|---|
| committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-08-22 20:30:15 -0400 |
| commit | 650171566bff59e9eb372f213fdce4dfbb6da5bd (patch) | |
| tree | f7125ce134cdb79ab0e35d70330ea79c8b11af2f /drivers/gpu/nvgpu/common/pmu/pmu_ipc.c | |
| parent | 138e70b0d40609b896ab576a8f0ea23e23c7825b (diff) | |
gpu: nvgpu: gv100: Fix nonpes aware tpc mapping
For gv1xx, kernel smid configuration programming is done based
on nonpes aware tpc. On gv100 the registers GPM_PD_SM_ID and SM_CFG
are indexed on nonpes aware tpc.
Bug 2096878
Change-Id: I0edc2f066e2c3b35057fde102689a9f1915c72ea
Signed-off-by: Philemon Gardet <pgardet@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1783046
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Sandarbh Jain <sanjain@nvidia.com>
Tested-by: Sandarbh Jain <sanjain@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/common/pmu/pmu_ipc.c')
0 files changed, 0 insertions, 0 deletions