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| author | Thomas Fleury <tfleury@nvidia.com> | 2017-10-19 13:16:39 -0400 |
|---|---|---|
| committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-10-25 01:07:32 -0400 |
| commit | 539c8bff4b501a4ca999290454a210f5d17ba516 (patch) | |
| tree | 294638bf3dbce6a39ed4c2be5193ffa6867db2eb /drivers/gpu/nvgpu/common/pmu/pmu_ipc.c | |
| parent | 0c5d0c6a9ef0e33f01ce1485674bb2271e4bb580 (diff) | |
gpu: nvgpu: use full system barrier in BAR1 test
BAR1 test could occasionally fail when doing CPU write through userd
then reading back through BAR1. This is because nvgpu_smp_mb() only
guarantees ordering between cores.
Replaced with nvgpu_mb() to ensure the write will be visible to all
bus masters in the system.
JIRA EVLR-1959
Bug 200352099
Change-Id: Id002e73d135e0805fca2f153a6de77e210a7b226
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1582928
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/common/pmu/pmu_ipc.c')
0 files changed, 0 insertions, 0 deletions