gpu: nvgpu: boardobj update for gv10x branch

- Created ops for below boardobj methods to support gp10x & gv10x
  branch boardobj changes, and defined methods for gv10x with
  postfix _v1 with below names
    boardobjgrp_pmucmd_construct_impl
    boardobjgrp_pmuset_impl
    boardobjgrp_pmugetstatus_impl
    is_boardobjgrp_pmucmd_id_valid
- These ops are assigned based on PMU version to respective
  chip.
- Modified BOARDOBJGRP_PMU_CMD_GRP_SET_CONSTRUCT &
  BOARDOBJGRP_PMU_CMD_GRP_GET_STATUS_CONSTRUCT to support
  gp10x & gv10x branch changes
- Updated struct boardobjgrp_pmu_cmd to include members
  needed for gv10x boardobj changes
- Created "struct nv_pmu_rpc_struct_board_obj_grp_cmd"
  to execute BOARD_OBJ_GRP_CMD using RPC.
- Defined method boardobjgrp_pmucmdsend_rpc() to
  send BOARD_OBJ_GRP_CMD to PMU.

Change-Id: If2551bdda80e897e7b21d2966881586f3bbc7a9b
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1656511
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 16 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_fw.c b/drivers/gpu/nvgpu/common/pmu/pmu_fw.c
index 6b565abb..20120393 100644
--- a/drivers/gpu/nvgpu/common/pmu/pmu_fw.c
+++ b/drivers/gpu/nvgpu/common/pmu/pmu_fw.c
@@ -1291,6 +1291,14 @@ static int nvgpu_init_pmu_fw_ver_ops(struct nvgpu_pmu *pmu)
                                 get_pmu_init_msg_pmu_sw_mg_off_v5;
                         g->ops.pmu_ver.get_pmu_init_msg_pmu_sw_mg_size =
                                 get_pmu_init_msg_pmu_sw_mg_size_v5;
+                        g->ops.pmu_ver.boardobj.boardobjgrp_pmucmd_construct_impl =
+                                boardobjgrp_pmucmd_construct_impl_v1;
+                        g->ops.pmu_ver.boardobj.boardobjgrp_pmuset_impl =
+                                boardobjgrp_pmuset_impl_v1;
+                        g->ops.pmu_ver.boardobj.boardobjgrp_pmugetstatus_impl =
+                                boardobjgrp_pmugetstatus_impl_v1;
+                        g->ops.pmu_ver.boardobj.is_boardobjgrp_pmucmd_id_valid =
+                                is_boardobjgrp_pmucmd_id_valid_v1;
                 } else {
                         g->ops.pmu_ver.get_pmu_init_msg_pmu_queue_params =
                                 get_pmu_init_msg_pmu_queue_params_v4;
@@ -1442,6 +1450,14 @@ static int nvgpu_init_pmu_fw_ver_ops(struct nvgpu_pmu *pmu)
                         get_pmu_sequence_in_alloc_ptr_v3;
                 g->ops.pmu_ver.get_pmu_seq_out_a_ptr =
                         get_pmu_sequence_out_alloc_ptr_v3;
+                g->ops.pmu_ver.boardobj.boardobjgrp_pmucmd_construct_impl =
+                        boardobjgrp_pmucmd_construct_impl;
+                g->ops.pmu_ver.boardobj.boardobjgrp_pmuset_impl =
+                        boardobjgrp_pmuset_impl;
+                g->ops.pmu_ver.boardobj.boardobjgrp_pmugetstatus_impl =
+                        boardobjgrp_pmugetstatus_impl;
+                g->ops.pmu_ver.boardobj.is_boardobjgrp_pmucmd_id_valid =
+                        is_boardobjgrp_pmucmd_id_valid_v0;
                 break;
         case APP_VERSION_GM20B:
                 g->ops.pmu_ver.pg_cmd_eng_buf_load_size =