gpu: nvgpu: Move non-fp pmu members from gpu_ops

Move non-function pointer members out of the pmu and pmu_ver
substructs of gpu_ops. Ideally gpu_ops will have only function
ponters, better matching its intended purpose and improving
readability.

 - g.ops.pmu_ver.cmd_id_zbc_table_update has been changed to
    g.pmu_ver_cmd_id_zbc_table_update
 - g.ops.pmu.lspmuwprinitdone has been changed to
    g.pmu_lsf_pmu_wpr_init_done
 - g.ops.pmu.lsfloadedfalconid has been changed to
    g.pmu_lsf_loaded_falcon_id

Boolean flags have been implemented using the enabled.h API
 - g.ops.pmu_ver.is_pmu_zbc_save_supported moved to
    common flag NVGPU_PMU_ZBC_SAVE
 - g.ops.pmu.fecsbootstrapdone moved to
    common flag NVGPU_PMU_FECS_BOOTSTRAP_DONE

Jira NVGPU-74

Change-Id: I08fb20f8f382277f2c579f06d561914c000ea6e0
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1530981
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

1 files changed, 15 insertions, 14 deletions

diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_fw.c b/drivers/gpu/nvgpu/common/pmu/pmu_fw.c
index f6229a3a..03c60449 100644
--- a/drivers/gpu/nvgpu/common/pmu/pmu_fw.c
+++ b/drivers/gpu/nvgpu/common/pmu/pmu_fw.c
@@ -16,6 +16,7 @@
 #include <nvgpu/log.h>
 #include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h>
 #include <nvgpu/firmware.h>
+#include <nvgpu/enabled.h>
 
 #include "gk20a/gk20a.h"
 
@@ -1463,8 +1464,8 @@ static int nvgpu_init_pmu_fw_ver_ops(struct nvgpu_pmu *pmu)
                 g->ops.pmu_ver.set_perfmon_cntr_group_id =
                         set_perfmon_cntr_group_id_v2;
                 g->ops.pmu_ver.get_perfmon_cntr_sz = pmu_perfmon_cntr_sz_v2;
-                g->ops.pmu_ver.cmd_id_zbc_table_update = 16;
-                g->ops.pmu_ver.is_pmu_zbc_save_supported = true;
+                g->pmu_ver_cmd_id_zbc_table_update = 16;
+                __nvgpu_set_enabled(g, NVGPU_PMU_ZBC_SAVE, true);
                 g->ops.pmu_ver.get_pmu_cmdline_args_size =
                         pmu_cmdline_size_v4;
                 g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq =
@@ -1565,8 +1566,8 @@ static int nvgpu_init_pmu_fw_ver_ops(struct nvgpu_pmu *pmu)
                 g->ops.pmu_ver.set_perfmon_cntr_group_id =
                         set_perfmon_cntr_group_id_v2;
                 g->ops.pmu_ver.get_perfmon_cntr_sz = pmu_perfmon_cntr_sz_v2;
-                g->ops.pmu_ver.cmd_id_zbc_table_update = 16;
-                g->ops.pmu_ver.is_pmu_zbc_save_supported = false;
+                g->pmu_ver_cmd_id_zbc_table_update = 16;
+                __nvgpu_set_enabled(g, NVGPU_PMU_ZBC_SAVE, false);
                 g->ops.pmu_ver.get_pmu_cmdline_args_size =
                         pmu_cmdline_size_v6;
                 g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq =
@@ -1673,8 +1674,8 @@ static int nvgpu_init_pmu_fw_ver_ops(struct nvgpu_pmu *pmu)
                 g->ops.pmu_ver.set_perfmon_cntr_group_id =
                         set_perfmon_cntr_group_id_v2;
                 g->ops.pmu_ver.get_perfmon_cntr_sz = pmu_perfmon_cntr_sz_v2;
-                g->ops.pmu_ver.cmd_id_zbc_table_update = 16;
-                g->ops.pmu_ver.is_pmu_zbc_save_supported = true;
+                g->pmu_ver_cmd_id_zbc_table_update = 16;
+                __nvgpu_set_enabled(g, NVGPU_PMU_ZBC_SAVE, true);
                 g->ops.pmu_ver.get_pmu_cmdline_args_size =
                         pmu_cmdline_size_v5;
                 g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq =
@@ -1792,8 +1793,8 @@ static int nvgpu_init_pmu_fw_ver_ops(struct nvgpu_pmu *pmu)
                 g->ops.pmu_ver.set_perfmon_cntr_group_id =
                         set_perfmon_cntr_group_id_v2;
                 g->ops.pmu_ver.get_perfmon_cntr_sz = pmu_perfmon_cntr_sz_v2;
-                g->ops.pmu_ver.cmd_id_zbc_table_update = 16;
-                g->ops.pmu_ver.is_pmu_zbc_save_supported = true;
+                g->pmu_ver_cmd_id_zbc_table_update = 16;
+                __nvgpu_set_enabled(g, NVGPU_PMU_ZBC_SAVE, true);
                 g->ops.pmu_ver.get_pmu_cmdline_args_size =
                         pmu_cmdline_size_v3;
                 g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq =
@@ -1895,8 +1896,8 @@ static int nvgpu_init_pmu_fw_ver_ops(struct nvgpu_pmu *pmu)
                 g->ops.pmu_ver.set_perfmon_cntr_group_id =
                         set_perfmon_cntr_group_id_v2;
                 g->ops.pmu_ver.get_perfmon_cntr_sz = pmu_perfmon_cntr_sz_v2;
-                g->ops.pmu_ver.cmd_id_zbc_table_update = 16;
-                g->ops.pmu_ver.is_pmu_zbc_save_supported = true;
+                g->pmu_ver_cmd_id_zbc_table_update = 16;
+                __nvgpu_set_enabled(g, NVGPU_PMU_ZBC_SAVE, true);
                 g->ops.pmu_ver.get_pmu_cmdline_args_size =
                         pmu_cmdline_size_v2;
                 g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq =
@@ -1991,8 +1992,8 @@ static int nvgpu_init_pmu_fw_ver_ops(struct nvgpu_pmu *pmu)
                                 pg_cmd_eng_buf_load_set_dma_offset_v0;
                 g->ops.pmu_ver.pg_cmd_eng_buf_load_set_dma_idx =
                                 pg_cmd_eng_buf_load_set_dma_idx_v0;
-                g->ops.pmu_ver.cmd_id_zbc_table_update = 16;
-                g->ops.pmu_ver.is_pmu_zbc_save_supported = true;
+                g->pmu_ver_cmd_id_zbc_table_update = 16;
+                __nvgpu_set_enabled(g, NVGPU_PMU_ZBC_SAVE, true);
                 g->ops.pmu_ver.get_perfmon_cntr_ptr = get_perfmon_cntr_ptr_v0;
                 g->ops.pmu_ver.set_perfmon_cntr_ut = set_perfmon_cntr_ut_v0;
                 g->ops.pmu_ver.set_perfmon_cntr_lt = set_perfmon_cntr_lt_v0;
@@ -2093,8 +2094,8 @@ static int nvgpu_init_pmu_fw_ver_ops(struct nvgpu_pmu *pmu)
                                 pg_cmd_eng_buf_load_set_dma_offset_v0;
                 g->ops.pmu_ver.pg_cmd_eng_buf_load_set_dma_idx =
                                 pg_cmd_eng_buf_load_set_dma_idx_v0;
-                g->ops.pmu_ver.cmd_id_zbc_table_update = 14;
-                g->ops.pmu_ver.is_pmu_zbc_save_supported = true;
+                g->pmu_ver_cmd_id_zbc_table_update = 14;
+                __nvgpu_set_enabled(g, NVGPU_PMU_ZBC_SAVE, true);
                 g->ops.pmu_ver.get_perfmon_cntr_ptr = get_perfmon_cntr_ptr_v0;
                 g->ops.pmu_ver.set_perfmon_cntr_ut = set_perfmon_cntr_ut_v0;
                 g->ops.pmu_ver.set_perfmon_cntr_lt = set_perfmon_cntr_lt_v0;