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authorMahantesh Kumbar <mkumbar@nvidia.com>2018-01-22 02:36:41 -0500
committermobile promotions <svcmobile_promotions@nvidia.com>2018-01-23 05:59:01 -0500
commit9f4cf27119199f95a1e33813426d0e9ba76dbf0c (patch)
tree4de2c71bffbe0a36c43b221bf3bf3117c1096d94 /drivers/gpu/nvgpu/common/pmu/pmu_fw.c
parentf3f14cdff53f4b936e2505d44aad6e3bca143056 (diff)
gpu: nvgpu: PMU code cleanup
-removed unsupported PMU f/w version defines & corrected naming specific to chip -removed unsupported PMU f/w version methods which are not useful for existing ucode. -removed unsupported PMU interface which are not useful for existing ucode Change-Id: I17933ff656f48a888e049d680f108b2ef7537439 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1643399 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/common/pmu/pmu_fw.c')
-rw-r--r--drivers/gpu/nvgpu/common/pmu/pmu_fw.c741
1 files changed, 15 insertions, 726 deletions
diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_fw.c b/drivers/gpu/nvgpu/common/pmu/pmu_fw.c
index 339d39b3..1c1a3c82 100644
--- a/drivers/gpu/nvgpu/common/pmu/pmu_fw.c
+++ b/drivers/gpu/nvgpu/common/pmu/pmu_fw.c
@@ -36,31 +36,13 @@
36#define NVGPU_PMU_NS_UCODE_IMAGE "gpmu_ucode.bin" 36#define NVGPU_PMU_NS_UCODE_IMAGE "gpmu_ucode.bin"
37 37
38/* PMU F/W version */ 38/* PMU F/W version */
39#define APP_VERSION_BIGGPU 22836594 39#define APP_VERSION_GV11B 23355380
40#define APP_VERSION_NC_3 23355380 40#define APP_VERSION_GV10X 22836594
41#define APP_VERSION_NC_2 20429989 41#define APP_VERSION_GP10X 21308030
42#define APP_VERSION_NC_1 20313802 42#define APP_VERSION_GP10B 20429989
43#define APP_VERSION_NC_0 20360931 43#define APP_VERSION_GM20B 20490253
44#define APP_VERSION_GM206 20652057
45#define APP_VERSION_NV_GPU 21307569
46#define APP_VERSION_NV_GPU_1 21308030
47#define APP_VERSION_GM20B_5 20490253
48#define APP_VERSION_GM20B_4 19008461
49#define APP_VERSION_GM20B_3 18935575
50#define APP_VERSION_GM20B_2 18694072
51#define APP_VERSION_GM20B_1 18547257
52#define APP_VERSION_GM20B 17615280
53#define APP_VERSION_3 18357968
54#define APP_VERSION_2 18542378
55#define APP_VERSION_1 17997577 /*Obsolete this once 18357968 gets in*/
56#define APP_VERSION_0 16856675
57 44
58/* PMU version specific functions */ 45/* PMU version specific functions */
59static u32 pmu_perfmon_cntr_sz_v0(struct nvgpu_pmu *pmu)
60{
61 return sizeof(struct pmu_perfmon_counter_v0);
62}
63
64static u32 pmu_perfmon_cntr_sz_v2(struct nvgpu_pmu *pmu) 46static u32 pmu_perfmon_cntr_sz_v2(struct nvgpu_pmu *pmu)
65{ 47{
66 return sizeof(struct pmu_perfmon_counter_v2); 48 return sizeof(struct pmu_perfmon_counter_v2);
@@ -71,103 +53,31 @@ static void *get_perfmon_cntr_ptr_v2(struct nvgpu_pmu *pmu)
71 return (void *)(&pmu->perfmon_counter_v2); 53 return (void *)(&pmu->perfmon_counter_v2);
72} 54}
73 55
74static void *get_perfmon_cntr_ptr_v0(struct nvgpu_pmu *pmu)
75{
76 return (void *)(&pmu->perfmon_counter_v0);
77}
78
79static void set_perfmon_cntr_ut_v2(struct nvgpu_pmu *pmu, u16 ut) 56static void set_perfmon_cntr_ut_v2(struct nvgpu_pmu *pmu, u16 ut)
80{ 57{
81 pmu->perfmon_counter_v2.upper_threshold = ut; 58 pmu->perfmon_counter_v2.upper_threshold = ut;
82} 59}
83 60
84static void set_perfmon_cntr_ut_v0(struct nvgpu_pmu *pmu, u16 ut)
85{
86 pmu->perfmon_counter_v0.upper_threshold = ut;
87}
88
89static void set_perfmon_cntr_lt_v2(struct nvgpu_pmu *pmu, u16 lt) 61static void set_perfmon_cntr_lt_v2(struct nvgpu_pmu *pmu, u16 lt)
90{ 62{
91 pmu->perfmon_counter_v2.lower_threshold = lt; 63 pmu->perfmon_counter_v2.lower_threshold = lt;
92} 64}
93 65
94static void set_perfmon_cntr_lt_v0(struct nvgpu_pmu *pmu, u16 lt)
95{
96 pmu->perfmon_counter_v0.lower_threshold = lt;
97}
98
99static void set_perfmon_cntr_valid_v2(struct nvgpu_pmu *pmu, u8 valid) 66static void set_perfmon_cntr_valid_v2(struct nvgpu_pmu *pmu, u8 valid)
100{ 67{
101 pmu->perfmon_counter_v2.valid = valid; 68 pmu->perfmon_counter_v2.valid = valid;
102} 69}
103 70
104static void set_perfmon_cntr_valid_v0(struct nvgpu_pmu *pmu, u8 valid)
105{
106 pmu->perfmon_counter_v0.valid = valid;
107}
108
109static void set_perfmon_cntr_index_v2(struct nvgpu_pmu *pmu, u8 index) 71static void set_perfmon_cntr_index_v2(struct nvgpu_pmu *pmu, u8 index)
110{ 72{
111 pmu->perfmon_counter_v2.index = index; 73 pmu->perfmon_counter_v2.index = index;
112} 74}
113 75
114static void set_perfmon_cntr_index_v0(struct nvgpu_pmu *pmu, u8 index)
115{
116 pmu->perfmon_counter_v0.index = index;
117}
118
119static void set_perfmon_cntr_group_id_v2(struct nvgpu_pmu *pmu, u8 gid) 76static void set_perfmon_cntr_group_id_v2(struct nvgpu_pmu *pmu, u8 gid)
120{ 77{
121 pmu->perfmon_counter_v2.group_id = gid; 78 pmu->perfmon_counter_v2.group_id = gid;
122} 79}
123 80
124static void set_perfmon_cntr_group_id_v0(struct nvgpu_pmu *pmu, u8 gid)
125{
126 pmu->perfmon_counter_v0.group_id = gid;
127}
128
129static u32 pmu_cmdline_size_v0(struct nvgpu_pmu *pmu)
130{
131 return sizeof(struct pmu_cmdline_args_v0);
132}
133
134static u32 pmu_cmdline_size_v1(struct nvgpu_pmu *pmu)
135{
136 return sizeof(struct pmu_cmdline_args_v1);
137}
138
139static u32 pmu_cmdline_size_v2(struct nvgpu_pmu *pmu)
140{
141 return sizeof(struct pmu_cmdline_args_v2);
142}
143
144static void set_pmu_cmdline_args_cpufreq_v2(struct nvgpu_pmu *pmu, u32 freq)
145{
146 pmu->args_v2.cpu_freq_hz = freq;
147}
148static void set_pmu_cmdline_args_secure_mode_v2(struct nvgpu_pmu *pmu, u32 val)
149{
150 pmu->args_v2.secure_mode = val;
151}
152
153static void set_pmu_cmdline_args_falctracesize_v2(
154 struct nvgpu_pmu *pmu, u32 size)
155{
156 pmu->args_v2.falc_trace_size = size;
157}
158
159static void set_pmu_cmdline_args_falctracedmabase_v2(struct nvgpu_pmu *pmu)
160{
161 pmu->args_v2.falc_trace_dma_base = ((u32)pmu->trace_buf.gpu_va)/0x100;
162}
163
164static void set_pmu_cmdline_args_falctracedmaidx_v2(
165 struct nvgpu_pmu *pmu, u32 idx)
166{
167 pmu->args_v2.falc_trace_dma_idx = idx;
168}
169
170
171static void set_pmu_cmdline_args_falctracedmabase_v4(struct nvgpu_pmu *pmu) 81static void set_pmu_cmdline_args_falctracedmabase_v4(struct nvgpu_pmu *pmu)
172{ 82{
173 pmu->args_v4.dma_addr.dma_base = ((u32)pmu->trace_buf.gpu_va)/0x100; 83 pmu->args_v4.dma_addr.dma_base = ((u32)pmu->trace_buf.gpu_va)/0x100;
@@ -269,37 +179,6 @@ static void set_pmu_cmdline_args_falctracedmaidx_v3(
269 pmu->args_v3.falc_trace_dma_idx = idx; 179 pmu->args_v3.falc_trace_dma_idx = idx;
270} 180}
271 181
272static void set_pmu_cmdline_args_cpufreq_v1(struct nvgpu_pmu *pmu, u32 freq)
273{
274 pmu->args_v1.cpu_freq_hz = freq;
275}
276static void set_pmu_cmdline_args_secure_mode_v1(struct nvgpu_pmu *pmu, u32 val)
277{
278 pmu->args_v1.secure_mode = val;
279}
280
281static void set_pmu_cmdline_args_falctracesize_v1(
282 struct nvgpu_pmu *pmu, u32 size)
283{
284 pmu->args_v1.falc_trace_size = size;
285}
286
287static void set_pmu_cmdline_args_falctracedmabase_v1(struct nvgpu_pmu *pmu)
288{
289 pmu->args_v1.falc_trace_dma_base = ((u32)pmu->trace_buf.gpu_va)/0x100;
290}
291
292static void set_pmu_cmdline_args_falctracedmaidx_v1(
293 struct nvgpu_pmu *pmu, u32 idx)
294{
295 pmu->args_v1.falc_trace_dma_idx = idx;
296}
297
298static void set_pmu_cmdline_args_cpufreq_v0(struct nvgpu_pmu *pmu, u32 freq)
299{
300 pmu->args_v0.cpu_freq_hz = freq;
301}
302
303static void *get_pmu_cmdline_args_ptr_v4(struct nvgpu_pmu *pmu) 182static void *get_pmu_cmdline_args_ptr_v4(struct nvgpu_pmu *pmu)
304{ 183{
305 return (void *)(&pmu->args_v4); 184 return (void *)(&pmu->args_v4);
@@ -310,24 +189,10 @@ static void *get_pmu_cmdline_args_ptr_v3(struct nvgpu_pmu *pmu)
310 return (void *)(&pmu->args_v3); 189 return (void *)(&pmu->args_v3);
311} 190}
312 191
313static void *get_pmu_cmdline_args_ptr_v2(struct nvgpu_pmu *pmu)
314{
315 return (void *)(&pmu->args_v2);
316}
317
318static void *get_pmu_cmdline_args_ptr_v5(struct nvgpu_pmu *pmu) 192static void *get_pmu_cmdline_args_ptr_v5(struct nvgpu_pmu *pmu)
319{ 193{
320 return (void *)(&pmu->args_v5); 194 return (void *)(&pmu->args_v5);
321} 195}
322static void *get_pmu_cmdline_args_ptr_v1(struct nvgpu_pmu *pmu)
323{
324 return (void *)(&pmu->args_v1);
325}
326
327static void *get_pmu_cmdline_args_ptr_v0(struct nvgpu_pmu *pmu)
328{
329 return (void *)(&pmu->args_v0);
330}
331 196
332static u32 get_pmu_allocation_size_v3(struct nvgpu_pmu *pmu) 197static u32 get_pmu_allocation_size_v3(struct nvgpu_pmu *pmu)
333{ 198{
@@ -344,11 +209,6 @@ static u32 get_pmu_allocation_size_v1(struct nvgpu_pmu *pmu)
344 return sizeof(struct pmu_allocation_v1); 209 return sizeof(struct pmu_allocation_v1);
345} 210}
346 211
347static u32 get_pmu_allocation_size_v0(struct nvgpu_pmu *pmu)
348{
349 return sizeof(struct pmu_allocation_v0);
350}
351
352static void set_pmu_allocation_ptr_v3(struct nvgpu_pmu *pmu, 212static void set_pmu_allocation_ptr_v3(struct nvgpu_pmu *pmu,
353 void **pmu_alloc_ptr, void *assign_ptr) 213 void **pmu_alloc_ptr, void *assign_ptr)
354{ 214{
@@ -376,15 +236,6 @@ static void set_pmu_allocation_ptr_v1(struct nvgpu_pmu *pmu,
376 *pmu_a_ptr = (struct pmu_allocation_v1 *)assign_ptr; 236 *pmu_a_ptr = (struct pmu_allocation_v1 *)assign_ptr;
377} 237}
378 238
379static void set_pmu_allocation_ptr_v0(struct nvgpu_pmu *pmu,
380 void **pmu_alloc_ptr, void *assign_ptr)
381{
382 struct pmu_allocation_v0 **pmu_a_ptr =
383 (struct pmu_allocation_v0 **)pmu_alloc_ptr;
384
385 *pmu_a_ptr = (struct pmu_allocation_v0 *)assign_ptr;
386}
387
388static void pmu_allocation_set_dmem_size_v3(struct nvgpu_pmu *pmu, 239static void pmu_allocation_set_dmem_size_v3(struct nvgpu_pmu *pmu,
389 void *pmu_alloc_ptr, u16 size) 240 void *pmu_alloc_ptr, u16 size)
390{ 241{
@@ -412,15 +263,6 @@ static void pmu_allocation_set_dmem_size_v1(struct nvgpu_pmu *pmu,
412 pmu_a_ptr->alloc.dmem.size = size; 263 pmu_a_ptr->alloc.dmem.size = size;
413} 264}
414 265
415static void pmu_allocation_set_dmem_size_v0(struct nvgpu_pmu *pmu,
416 void *pmu_alloc_ptr, u16 size)
417{
418 struct pmu_allocation_v0 *pmu_a_ptr =
419 (struct pmu_allocation_v0 *)pmu_alloc_ptr;
420
421 pmu_a_ptr->alloc.dmem.size = size;
422}
423
424static u16 pmu_allocation_get_dmem_size_v3(struct nvgpu_pmu *pmu, 266static u16 pmu_allocation_get_dmem_size_v3(struct nvgpu_pmu *pmu,
425 void *pmu_alloc_ptr) 267 void *pmu_alloc_ptr)
426{ 268{
@@ -448,15 +290,6 @@ static u16 pmu_allocation_get_dmem_size_v1(struct nvgpu_pmu *pmu,
448 return pmu_a_ptr->alloc.dmem.size; 290 return pmu_a_ptr->alloc.dmem.size;
449} 291}
450 292
451static u16 pmu_allocation_get_dmem_size_v0(struct nvgpu_pmu *pmu,
452 void *pmu_alloc_ptr)
453{
454 struct pmu_allocation_v0 *pmu_a_ptr =
455 (struct pmu_allocation_v0 *)pmu_alloc_ptr;
456
457 return pmu_a_ptr->alloc.dmem.size;
458}
459
460static u32 pmu_allocation_get_dmem_offset_v3(struct nvgpu_pmu *pmu, 293static u32 pmu_allocation_get_dmem_offset_v3(struct nvgpu_pmu *pmu,
461 void *pmu_alloc_ptr) 294 void *pmu_alloc_ptr)
462{ 295{
@@ -484,15 +317,6 @@ static u32 pmu_allocation_get_dmem_offset_v1(struct nvgpu_pmu *pmu,
484 return pmu_a_ptr->alloc.dmem.offset; 317 return pmu_a_ptr->alloc.dmem.offset;
485} 318}
486 319
487static u32 pmu_allocation_get_dmem_offset_v0(struct nvgpu_pmu *pmu,
488 void *pmu_alloc_ptr)
489{
490 struct pmu_allocation_v0 *pmu_a_ptr =
491 (struct pmu_allocation_v0 *)pmu_alloc_ptr;
492
493 return pmu_a_ptr->alloc.dmem.offset;
494}
495
496static u32 *pmu_allocation_get_dmem_offset_addr_v3(struct nvgpu_pmu *pmu, 320static u32 *pmu_allocation_get_dmem_offset_addr_v3(struct nvgpu_pmu *pmu,
497 void *pmu_alloc_ptr) 321 void *pmu_alloc_ptr)
498{ 322{
@@ -538,15 +362,6 @@ static u32 *pmu_allocation_get_dmem_offset_addr_v1(struct nvgpu_pmu *pmu,
538 return &pmu_a_ptr->alloc.dmem.offset; 362 return &pmu_a_ptr->alloc.dmem.offset;
539} 363}
540 364
541static u32 *pmu_allocation_get_dmem_offset_addr_v0(struct nvgpu_pmu *pmu,
542 void *pmu_alloc_ptr)
543{
544 struct pmu_allocation_v0 *pmu_a_ptr =
545 (struct pmu_allocation_v0 *)pmu_alloc_ptr;
546
547 return &pmu_a_ptr->alloc.dmem.offset;
548}
549
550static void pmu_allocation_set_dmem_offset_v3(struct nvgpu_pmu *pmu, 365static void pmu_allocation_set_dmem_offset_v3(struct nvgpu_pmu *pmu,
551 void *pmu_alloc_ptr, u32 offset) 366 void *pmu_alloc_ptr, u32 offset)
552{ 367{
@@ -574,15 +389,6 @@ static void pmu_allocation_set_dmem_offset_v1(struct nvgpu_pmu *pmu,
574 pmu_a_ptr->alloc.dmem.offset = offset; 389 pmu_a_ptr->alloc.dmem.offset = offset;
575} 390}
576 391
577static void pmu_allocation_set_dmem_offset_v0(struct nvgpu_pmu *pmu,
578 void *pmu_alloc_ptr, u32 offset)
579{
580 struct pmu_allocation_v0 *pmu_a_ptr =
581 (struct pmu_allocation_v0 *)pmu_alloc_ptr;
582
583 pmu_a_ptr->alloc.dmem.offset = offset;
584}
585
586static void *get_pmu_msg_pmu_init_msg_ptr_v4(struct pmu_init_msg *init) 392static void *get_pmu_msg_pmu_init_msg_ptr_v4(struct pmu_init_msg *init)
587{ 393{
588 return (void *)(&(init->pmu_init_v4)); 394 return (void *)(&(init->pmu_init_v4));
@@ -625,27 +431,6 @@ static u16 get_pmu_init_msg_pmu_sw_mg_size_v3(union pmu_init_msg_pmu *init_msg)
625 return init->sw_managed_area_size; 431 return init->sw_managed_area_size;
626} 432}
627 433
628static void *get_pmu_msg_pmu_init_msg_ptr_v2(struct pmu_init_msg *init)
629{
630 return (void *)(&(init->pmu_init_v2));
631}
632
633static u16 get_pmu_init_msg_pmu_sw_mg_off_v2(union pmu_init_msg_pmu *init_msg)
634{
635 struct pmu_init_msg_pmu_v2 *init =
636 (struct pmu_init_msg_pmu_v2 *)(&init_msg->v1);
637
638 return init->sw_managed_area_offset;
639}
640
641static u16 get_pmu_init_msg_pmu_sw_mg_size_v2(union pmu_init_msg_pmu *init_msg)
642{
643 struct pmu_init_msg_pmu_v2 *init =
644 (struct pmu_init_msg_pmu_v2 *)(&init_msg->v1);
645
646 return init->sw_managed_area_size;
647}
648
649static void *get_pmu_msg_pmu_init_msg_ptr_v1(struct pmu_init_msg *init) 434static void *get_pmu_msg_pmu_init_msg_ptr_v1(struct pmu_init_msg *init)
650{ 435{
651 return (void *)(&(init->pmu_init_v1)); 436 return (void *)(&(init->pmu_init_v1));
@@ -667,27 +452,6 @@ static u16 get_pmu_init_msg_pmu_sw_mg_size_v1(union pmu_init_msg_pmu *init_msg)
667 return init->sw_managed_area_size; 452 return init->sw_managed_area_size;
668} 453}
669 454
670static void *get_pmu_msg_pmu_init_msg_ptr_v0(struct pmu_init_msg *init)
671{
672 return (void *)(&(init->pmu_init_v0));
673}
674
675static u16 get_pmu_init_msg_pmu_sw_mg_off_v0(union pmu_init_msg_pmu *init_msg)
676{
677 struct pmu_init_msg_pmu_v0 *init =
678 (struct pmu_init_msg_pmu_v0 *)(&init_msg->v0);
679
680 return init->sw_managed_area_offset;
681}
682
683static u16 get_pmu_init_msg_pmu_sw_mg_size_v0(union pmu_init_msg_pmu *init_msg)
684{
685 struct pmu_init_msg_pmu_v0 *init =
686 (struct pmu_init_msg_pmu_v0 *)(&init_msg->v0);
687
688 return init->sw_managed_area_size;
689}
690
691static u32 get_pmu_perfmon_cmd_start_size_v3(void) 455static u32 get_pmu_perfmon_cmd_start_size_v3(void)
692{ 456{
693 return sizeof(struct pmu_perfmon_cmd_start_v3); 457 return sizeof(struct pmu_perfmon_cmd_start_v3);
@@ -703,11 +467,6 @@ static u32 get_pmu_perfmon_cmd_start_size_v1(void)
703 return sizeof(struct pmu_perfmon_cmd_start_v1); 467 return sizeof(struct pmu_perfmon_cmd_start_v1);
704} 468}
705 469
706static u32 get_pmu_perfmon_cmd_start_size_v0(void)
707{
708 return sizeof(struct pmu_perfmon_cmd_start_v0);
709}
710
711static int get_perfmon_cmd_start_offsetofvar_v3( 470static int get_perfmon_cmd_start_offsetofvar_v3(
712 enum pmu_perfmon_cmd_start_fields field) 471 enum pmu_perfmon_cmd_start_fields field)
713{ 472{
@@ -750,20 +509,6 @@ static int get_perfmon_cmd_start_offsetofvar_v1(
750 return 0; 509 return 0;
751} 510}
752 511
753static int get_perfmon_cmd_start_offsetofvar_v0(
754 enum pmu_perfmon_cmd_start_fields field)
755{
756 switch (field) {
757 case COUNTER_ALLOC:
758 return offsetof(struct pmu_perfmon_cmd_start_v0,
759 counter_alloc);
760 default:
761 return -EINVAL;
762 }
763
764 return 0;
765}
766
767static u32 get_pmu_perfmon_cmd_init_size_v3(void) 512static u32 get_pmu_perfmon_cmd_init_size_v3(void)
768{ 513{
769 return sizeof(struct pmu_perfmon_cmd_init_v3); 514 return sizeof(struct pmu_perfmon_cmd_init_v3);
@@ -779,11 +524,6 @@ static u32 get_pmu_perfmon_cmd_init_size_v1(void)
779 return sizeof(struct pmu_perfmon_cmd_init_v1); 524 return sizeof(struct pmu_perfmon_cmd_init_v1);
780} 525}
781 526
782static u32 get_pmu_perfmon_cmd_init_size_v0(void)
783{
784 return sizeof(struct pmu_perfmon_cmd_init_v0);
785}
786
787static int get_perfmon_cmd_init_offsetofvar_v3( 527static int get_perfmon_cmd_init_offsetofvar_v3(
788 enum pmu_perfmon_cmd_start_fields field) 528 enum pmu_perfmon_cmd_start_fields field)
789{ 529{
@@ -826,20 +566,6 @@ static int get_perfmon_cmd_init_offsetofvar_v1(
826 return 0; 566 return 0;
827} 567}
828 568
829static int get_perfmon_cmd_init_offsetofvar_v0(
830 enum pmu_perfmon_cmd_start_fields field)
831{
832 switch (field) {
833 case COUNTER_ALLOC:
834 return offsetof(struct pmu_perfmon_cmd_init_v0,
835 counter_alloc);
836 default:
837 return -EINVAL;
838 }
839
840 return 0;
841}
842
843static void perfmon_start_set_cmd_type_v3(struct pmu_perfmon_cmd *pc, u8 value) 569static void perfmon_start_set_cmd_type_v3(struct pmu_perfmon_cmd *pc, u8 value)
844{ 570{
845 struct pmu_perfmon_cmd_start_v3 *start = &pc->start_v3; 571 struct pmu_perfmon_cmd_start_v3 *start = &pc->start_v3;
@@ -861,13 +587,6 @@ static void perfmon_start_set_cmd_type_v1(struct pmu_perfmon_cmd *pc, u8 value)
861 start->cmd_type = value; 587 start->cmd_type = value;
862} 588}
863 589
864static void perfmon_start_set_cmd_type_v0(struct pmu_perfmon_cmd *pc, u8 value)
865{
866 struct pmu_perfmon_cmd_start_v0 *start = &pc->start_v0;
867
868 start->cmd_type = value;
869}
870
871static void perfmon_start_set_group_id_v3(struct pmu_perfmon_cmd *pc, u8 value) 590static void perfmon_start_set_group_id_v3(struct pmu_perfmon_cmd *pc, u8 value)
872{ 591{
873 struct pmu_perfmon_cmd_start_v3 *start = &pc->start_v3; 592 struct pmu_perfmon_cmd_start_v3 *start = &pc->start_v3;
@@ -889,13 +608,6 @@ static void perfmon_start_set_group_id_v1(struct pmu_perfmon_cmd *pc, u8 value)
889 start->group_id = value; 608 start->group_id = value;
890} 609}
891 610
892static void perfmon_start_set_group_id_v0(struct pmu_perfmon_cmd *pc, u8 value)
893{
894 struct pmu_perfmon_cmd_start_v0 *start = &pc->start_v0;
895
896 start->group_id = value;
897}
898
899static void perfmon_start_set_state_id_v3(struct pmu_perfmon_cmd *pc, u8 value) 611static void perfmon_start_set_state_id_v3(struct pmu_perfmon_cmd *pc, u8 value)
900{ 612{
901 struct pmu_perfmon_cmd_start_v3 *start = &pc->start_v3; 613 struct pmu_perfmon_cmd_start_v3 *start = &pc->start_v3;
@@ -917,13 +629,6 @@ static void perfmon_start_set_state_id_v1(struct pmu_perfmon_cmd *pc, u8 value)
917 start->state_id = value; 629 start->state_id = value;
918} 630}
919 631
920static void perfmon_start_set_state_id_v0(struct pmu_perfmon_cmd *pc, u8 value)
921{
922 struct pmu_perfmon_cmd_start_v0 *start = &pc->start_v0;
923
924 start->state_id = value;
925}
926
927static void perfmon_start_set_flags_v3(struct pmu_perfmon_cmd *pc, u8 value) 632static void perfmon_start_set_flags_v3(struct pmu_perfmon_cmd *pc, u8 value)
928{ 633{
929 struct pmu_perfmon_cmd_start_v3 *start = &pc->start_v3; 634 struct pmu_perfmon_cmd_start_v3 *start = &pc->start_v3;
@@ -945,13 +650,6 @@ static void perfmon_start_set_flags_v1(struct pmu_perfmon_cmd *pc, u8 value)
945 start->flags = value; 650 start->flags = value;
946} 651}
947 652
948static void perfmon_start_set_flags_v0(struct pmu_perfmon_cmd *pc, u8 value)
949{
950 struct pmu_perfmon_cmd_start_v0 *start = &pc->start_v0;
951
952 start->flags = value;
953}
954
955static u8 perfmon_start_get_flags_v3(struct pmu_perfmon_cmd *pc) 653static u8 perfmon_start_get_flags_v3(struct pmu_perfmon_cmd *pc)
956{ 654{
957 struct pmu_perfmon_cmd_start_v3 *start = &pc->start_v3; 655 struct pmu_perfmon_cmd_start_v3 *start = &pc->start_v3;
@@ -973,13 +671,6 @@ static u8 perfmon_start_get_flags_v1(struct pmu_perfmon_cmd *pc)
973 return start->flags; 671 return start->flags;
974} 672}
975 673
976static u8 perfmon_start_get_flags_v0(struct pmu_perfmon_cmd *pc)
977{
978 struct pmu_perfmon_cmd_start_v0 *start = &pc->start_v0;
979
980 return start->flags;
981}
982
983static void perfmon_cmd_init_set_sample_buffer_v3(struct pmu_perfmon_cmd *pc, 674static void perfmon_cmd_init_set_sample_buffer_v3(struct pmu_perfmon_cmd *pc,
984 u16 value) 675 u16 value)
985{ 676{
@@ -1005,14 +696,6 @@ static void perfmon_cmd_init_set_sample_buffer_v1(struct pmu_perfmon_cmd *pc,
1005 init->sample_buffer = value; 696 init->sample_buffer = value;
1006} 697}
1007 698
1008static void perfmon_cmd_init_set_sample_buffer_v0(struct pmu_perfmon_cmd *pc,
1009 u16 value)
1010{
1011 struct pmu_perfmon_cmd_init_v0 *init = &pc->init_v0;
1012
1013 init->sample_buffer = value;
1014}
1015
1016static void perfmon_cmd_init_set_dec_cnt_v3(struct pmu_perfmon_cmd *pc, 699static void perfmon_cmd_init_set_dec_cnt_v3(struct pmu_perfmon_cmd *pc,
1017 u8 value) 700 u8 value)
1018{ 701{
@@ -1037,14 +720,6 @@ static void perfmon_cmd_init_set_dec_cnt_v1(struct pmu_perfmon_cmd *pc,
1037 init->to_decrease_count = value; 720 init->to_decrease_count = value;
1038} 721}
1039 722
1040static void perfmon_cmd_init_set_dec_cnt_v0(struct pmu_perfmon_cmd *pc,
1041 u8 value)
1042{
1043 struct pmu_perfmon_cmd_init_v0 *init = &pc->init_v0;
1044
1045 init->to_decrease_count = value;
1046}
1047
1048static void perfmon_cmd_init_set_base_cnt_id_v3(struct pmu_perfmon_cmd *pc, 723static void perfmon_cmd_init_set_base_cnt_id_v3(struct pmu_perfmon_cmd *pc,
1049 u8 value) 724 u8 value)
1050{ 725{
@@ -1069,14 +744,6 @@ static void perfmon_cmd_init_set_base_cnt_id_v1(struct pmu_perfmon_cmd *pc,
1069 init->base_counter_id = value; 744 init->base_counter_id = value;
1070} 745}
1071 746
1072static void perfmon_cmd_init_set_base_cnt_id_v0(struct pmu_perfmon_cmd *pc,
1073 u8 value)
1074{
1075 struct pmu_perfmon_cmd_init_v0 *init = &pc->init_v0;
1076
1077 init->base_counter_id = value;
1078}
1079
1080static void perfmon_cmd_init_set_samp_period_us_v3(struct pmu_perfmon_cmd *pc, 747static void perfmon_cmd_init_set_samp_period_us_v3(struct pmu_perfmon_cmd *pc,
1081 u32 value) 748 u32 value)
1082{ 749{
@@ -1101,14 +768,6 @@ static void perfmon_cmd_init_set_samp_period_us_v1(struct pmu_perfmon_cmd *pc,
1101 init->sample_period_us = value; 768 init->sample_period_us = value;
1102} 769}
1103 770
1104static void perfmon_cmd_init_set_samp_period_us_v0(struct pmu_perfmon_cmd *pc,
1105 u32 value)
1106{
1107 struct pmu_perfmon_cmd_init_v0 *init = &pc->init_v0;
1108
1109 init->sample_period_us = value;
1110}
1111
1112static void perfmon_cmd_init_set_num_cnt_v3(struct pmu_perfmon_cmd *pc, 771static void perfmon_cmd_init_set_num_cnt_v3(struct pmu_perfmon_cmd *pc,
1113 u8 value) 772 u8 value)
1114{ 773{
@@ -1133,14 +792,6 @@ static void perfmon_cmd_init_set_num_cnt_v1(struct pmu_perfmon_cmd *pc,
1133 init->num_counters = value; 792 init->num_counters = value;
1134} 793}
1135 794
1136static void perfmon_cmd_init_set_num_cnt_v0(struct pmu_perfmon_cmd *pc,
1137 u8 value)
1138{
1139 struct pmu_perfmon_cmd_init_v0 *init = &pc->init_v0;
1140
1141 init->num_counters = value;
1142}
1143
1144static void perfmon_cmd_init_set_mov_avg_v3(struct pmu_perfmon_cmd *pc, 795static void perfmon_cmd_init_set_mov_avg_v3(struct pmu_perfmon_cmd *pc,
1145 u8 value) 796 u8 value)
1146{ 797{
@@ -1165,25 +816,6 @@ static void perfmon_cmd_init_set_mov_avg_v1(struct pmu_perfmon_cmd *pc,
1165 init->samples_in_moving_avg = value; 816 init->samples_in_moving_avg = value;
1166} 817}
1167 818
1168static void perfmon_cmd_init_set_mov_avg_v0(struct pmu_perfmon_cmd *pc,
1169 u8 value)
1170{
1171 struct pmu_perfmon_cmd_init_v0 *init = &pc->init_v0;
1172
1173 init->samples_in_moving_avg = value;
1174}
1175
1176static void get_pmu_init_msg_pmu_queue_params_v0(struct pmu_queue *queue,
1177 u32 id, void *pmu_init_msg)
1178{
1179 struct pmu_init_msg_pmu_v0 *init =
1180 (struct pmu_init_msg_pmu_v0 *)pmu_init_msg;
1181
1182 queue->index = init->queue_info[id].index;
1183 queue->offset = init->queue_info[id].offset;
1184 queue->size = init->queue_info[id].size;
1185}
1186
1187static void get_pmu_init_msg_pmu_queue_params_v1(struct pmu_queue *queue, 819static void get_pmu_init_msg_pmu_queue_params_v1(struct pmu_queue *queue,
1188 u32 id, void *pmu_init_msg) 820 u32 id, void *pmu_init_msg)
1189{ 821{
@@ -1195,17 +827,6 @@ static void get_pmu_init_msg_pmu_queue_params_v1(struct pmu_queue *queue,
1195 queue->size = init->queue_info[id].size; 827 queue->size = init->queue_info[id].size;
1196} 828}
1197 829
1198static void get_pmu_init_msg_pmu_queue_params_v2(struct pmu_queue *queue,
1199 u32 id, void *pmu_init_msg)
1200{
1201 struct pmu_init_msg_pmu_v2 *init =
1202 (struct pmu_init_msg_pmu_v2 *)pmu_init_msg;
1203
1204 queue->index = init->queue_info[id].index;
1205 queue->offset = init->queue_info[id].offset;
1206 queue->size = init->queue_info[id].size;
1207}
1208
1209static void get_pmu_init_msg_pmu_queue_params_v4(struct pmu_queue *queue, 830static void get_pmu_init_msg_pmu_queue_params_v4(struct pmu_queue *queue,
1210 u32 id, void *pmu_init_msg) 831 u32 id, void *pmu_init_msg)
1211{ 832{
@@ -1294,11 +915,6 @@ static void *get_pmu_sequence_in_alloc_ptr_v1(struct pmu_sequence *seq)
1294 return (void *)(&seq->in_v1); 915 return (void *)(&seq->in_v1);
1295} 916}
1296 917
1297static void *get_pmu_sequence_in_alloc_ptr_v0(struct pmu_sequence *seq)
1298{
1299 return (void *)(&seq->in_v0);
1300}
1301
1302static void *get_pmu_sequence_out_alloc_ptr_v3(struct pmu_sequence *seq) 918static void *get_pmu_sequence_out_alloc_ptr_v3(struct pmu_sequence *seq)
1303{ 919{
1304 return (void *)(&seq->out_v3); 920 return (void *)(&seq->out_v3);
@@ -1309,11 +925,6 @@ static void *get_pmu_sequence_out_alloc_ptr_v1(struct pmu_sequence *seq)
1309 return (void *)(&seq->out_v1); 925 return (void *)(&seq->out_v1);
1310} 926}
1311 927
1312static void *get_pmu_sequence_out_alloc_ptr_v0(struct pmu_sequence *seq)
1313{
1314 return (void *)(&seq->out_v0);
1315}
1316
1317static u8 pg_cmd_eng_buf_load_size_v0(struct pmu_pg_cmd *pg) 928static u8 pg_cmd_eng_buf_load_size_v0(struct pmu_pg_cmd *pg)
1318{ 929{
1319 return sizeof(pg->eng_buf_load_v0); 930 return sizeof(pg->eng_buf_load_v0);
@@ -1472,9 +1083,7 @@ static int nvgpu_init_pmu_fw_ver_ops(struct nvgpu_pmu *pmu)
1472 nvgpu_log_fn(g, " "); 1083 nvgpu_log_fn(g, " ");
1473 1084
1474 switch (pmu->desc->app_version) { 1085 switch (pmu->desc->app_version) {
1475 case APP_VERSION_NC_2: 1086 case APP_VERSION_GP10B:
1476 case APP_VERSION_NC_1:
1477 case APP_VERSION_NC_0:
1478 g->ops.pmu_ver.pg_cmd_eng_buf_load_size = 1087 g->ops.pmu_ver.pg_cmd_eng_buf_load_size =
1479 pg_cmd_eng_buf_load_size_v1; 1088 pg_cmd_eng_buf_load_size_v1;
1480 g->ops.pmu_ver.pg_cmd_eng_buf_load_set_cmd_type = 1089 g->ops.pmu_ver.pg_cmd_eng_buf_load_set_cmd_type =
@@ -1576,8 +1185,8 @@ static int nvgpu_init_pmu_fw_ver_ops(struct nvgpu_pmu *pmu)
1576 g->ops.pmu_ver.get_pmu_seq_out_a_ptr = 1185 g->ops.pmu_ver.get_pmu_seq_out_a_ptr =
1577 get_pmu_sequence_out_alloc_ptr_v1; 1186 get_pmu_sequence_out_alloc_ptr_v1;
1578 break; 1187 break;
1579 case APP_VERSION_NC_3: 1188 case APP_VERSION_GV11B:
1580 case APP_VERSION_BIGGPU: 1189 case APP_VERSION_GV10X:
1581 g->ops.pmu_ver.pg_cmd_eng_buf_load_size = 1190 g->ops.pmu_ver.pg_cmd_eng_buf_load_size =
1582 pg_cmd_eng_buf_load_size_v2; 1191 pg_cmd_eng_buf_load_size_v2;
1583 g->ops.pmu_ver.pg_cmd_eng_buf_load_set_cmd_type = 1192 g->ops.pmu_ver.pg_cmd_eng_buf_load_set_cmd_type =
@@ -1640,7 +1249,7 @@ static int nvgpu_init_pmu_fw_ver_ops(struct nvgpu_pmu *pmu)
1640 pmu_allocation_get_fb_addr_v3; 1249 pmu_allocation_get_fb_addr_v3;
1641 g->ops.pmu_ver.pmu_allocation_get_fb_size = 1250 g->ops.pmu_ver.pmu_allocation_get_fb_size =
1642 pmu_allocation_get_fb_size_v3; 1251 pmu_allocation_get_fb_size_v3;
1643 if (pmu->desc->app_version == APP_VERSION_BIGGPU) 1252 if (pmu->desc->app_version == APP_VERSION_GV10X)
1644 g->ops.pmu_ver.get_pmu_init_msg_pmu_queue_params = 1253 g->ops.pmu_ver.get_pmu_init_msg_pmu_queue_params =
1645 get_pmu_init_msg_pmu_queue_params_v5; 1254 get_pmu_init_msg_pmu_queue_params_v5;
1646 else 1255 else
@@ -1687,9 +1296,7 @@ static int nvgpu_init_pmu_fw_ver_ops(struct nvgpu_pmu *pmu)
1687 g->ops.pmu_ver.get_pmu_seq_out_a_ptr = 1296 g->ops.pmu_ver.get_pmu_seq_out_a_ptr =
1688 get_pmu_sequence_out_alloc_ptr_v3; 1297 get_pmu_sequence_out_alloc_ptr_v3;
1689 break; 1298 break;
1690 case APP_VERSION_GM206: 1299 case APP_VERSION_GP10X:
1691 case APP_VERSION_NV_GPU:
1692 case APP_VERSION_NV_GPU_1:
1693 g->ops.pmu_ver.pg_cmd_eng_buf_load_size = 1300 g->ops.pmu_ver.pg_cmd_eng_buf_load_size =
1694 pg_cmd_eng_buf_load_size_v2; 1301 pg_cmd_eng_buf_load_size_v2;
1695 g->ops.pmu_ver.pg_cmd_eng_buf_load_set_cmd_type = 1302 g->ops.pmu_ver.pg_cmd_eng_buf_load_set_cmd_type =
@@ -1752,26 +1359,14 @@ static int nvgpu_init_pmu_fw_ver_ops(struct nvgpu_pmu *pmu)
1752 pmu_allocation_get_fb_addr_v3; 1359 pmu_allocation_get_fb_addr_v3;
1753 g->ops.pmu_ver.pmu_allocation_get_fb_size = 1360 g->ops.pmu_ver.pmu_allocation_get_fb_size =
1754 pmu_allocation_get_fb_size_v3; 1361 pmu_allocation_get_fb_size_v3;
1755 if (pmu->desc->app_version != APP_VERSION_NV_GPU && 1362 g->ops.pmu_ver.get_pmu_init_msg_pmu_queue_params =
1756 pmu->desc->app_version != APP_VERSION_NV_GPU_1) {
1757 g->ops.pmu_ver.get_pmu_init_msg_pmu_queue_params =
1758 get_pmu_init_msg_pmu_queue_params_v2;
1759 g->ops.pmu_ver.get_pmu_msg_pmu_init_msg_ptr =
1760 get_pmu_msg_pmu_init_msg_ptr_v2;
1761 g->ops.pmu_ver.get_pmu_init_msg_pmu_sw_mg_off =
1762 get_pmu_init_msg_pmu_sw_mg_off_v2;
1763 g->ops.pmu_ver.get_pmu_init_msg_pmu_sw_mg_size =
1764 get_pmu_init_msg_pmu_sw_mg_size_v2;
1765 } else {
1766 g->ops.pmu_ver.get_pmu_init_msg_pmu_queue_params =
1767 get_pmu_init_msg_pmu_queue_params_v3; 1363 get_pmu_init_msg_pmu_queue_params_v3;
1768 g->ops.pmu_ver.get_pmu_msg_pmu_init_msg_ptr = 1364 g->ops.pmu_ver.get_pmu_msg_pmu_init_msg_ptr =
1769 get_pmu_msg_pmu_init_msg_ptr_v3; 1365 get_pmu_msg_pmu_init_msg_ptr_v3;
1770 g->ops.pmu_ver.get_pmu_init_msg_pmu_sw_mg_off = 1366 g->ops.pmu_ver.get_pmu_init_msg_pmu_sw_mg_off =
1771 get_pmu_init_msg_pmu_sw_mg_off_v3; 1367 get_pmu_init_msg_pmu_sw_mg_off_v3;
1772 g->ops.pmu_ver.get_pmu_init_msg_pmu_sw_mg_size = 1368 g->ops.pmu_ver.get_pmu_init_msg_pmu_sw_mg_size =
1773 get_pmu_init_msg_pmu_sw_mg_size_v3; 1369 get_pmu_init_msg_pmu_sw_mg_size_v3;
1774 }
1775 g->ops.pmu_ver.get_pmu_perfmon_cmd_start_size = 1370 g->ops.pmu_ver.get_pmu_perfmon_cmd_start_size =
1776 get_pmu_perfmon_cmd_start_size_v3; 1371 get_pmu_perfmon_cmd_start_size_v3;
1777 g->ops.pmu_ver.get_perfmon_cmd_start_offsetofvar = 1372 g->ops.pmu_ver.get_perfmon_cmd_start_offsetofvar =
@@ -1807,8 +1402,7 @@ static int nvgpu_init_pmu_fw_ver_ops(struct nvgpu_pmu *pmu)
1807 g->ops.pmu_ver.get_pmu_seq_out_a_ptr = 1402 g->ops.pmu_ver.get_pmu_seq_out_a_ptr =
1808 get_pmu_sequence_out_alloc_ptr_v3; 1403 get_pmu_sequence_out_alloc_ptr_v3;
1809 break; 1404 break;
1810 case APP_VERSION_GM20B_5: 1405 case APP_VERSION_GM20B:
1811 case APP_VERSION_GM20B_4:
1812 g->ops.pmu_ver.pg_cmd_eng_buf_load_size = 1406 g->ops.pmu_ver.pg_cmd_eng_buf_load_size =
1813 pg_cmd_eng_buf_load_size_v0; 1407 pg_cmd_eng_buf_load_size_v0;
1814 g->ops.pmu_ver.pg_cmd_eng_buf_load_set_cmd_type = 1408 g->ops.pmu_ver.pg_cmd_eng_buf_load_set_cmd_type =
@@ -1910,311 +1504,6 @@ static int nvgpu_init_pmu_fw_ver_ops(struct nvgpu_pmu *pmu)
1910 g->ops.pmu_ver.get_pmu_seq_out_a_ptr = 1504 g->ops.pmu_ver.get_pmu_seq_out_a_ptr =
1911 get_pmu_sequence_out_alloc_ptr_v1; 1505 get_pmu_sequence_out_alloc_ptr_v1;
1912 break; 1506 break;
1913 case APP_VERSION_GM20B_3:
1914 case APP_VERSION_GM20B_2:
1915 g->ops.pmu_ver.pg_cmd_eng_buf_load_size =
1916 pg_cmd_eng_buf_load_size_v0;
1917 g->ops.pmu_ver.pg_cmd_eng_buf_load_set_cmd_type =
1918 pg_cmd_eng_buf_load_set_cmd_type_v0;
1919 g->ops.pmu_ver.pg_cmd_eng_buf_load_set_engine_id =
1920 pg_cmd_eng_buf_load_set_engine_id_v0;
1921 g->ops.pmu_ver.pg_cmd_eng_buf_load_set_buf_idx =
1922 pg_cmd_eng_buf_load_set_buf_idx_v0;
1923 g->ops.pmu_ver.pg_cmd_eng_buf_load_set_pad =
1924 pg_cmd_eng_buf_load_set_pad_v0;
1925 g->ops.pmu_ver.pg_cmd_eng_buf_load_set_buf_size =
1926 pg_cmd_eng_buf_load_set_buf_size_v0;
1927 g->ops.pmu_ver.pg_cmd_eng_buf_load_set_dma_base =
1928 pg_cmd_eng_buf_load_set_dma_base_v0;
1929 g->ops.pmu_ver.pg_cmd_eng_buf_load_set_dma_offset =
1930 pg_cmd_eng_buf_load_set_dma_offset_v0;
1931 g->ops.pmu_ver.pg_cmd_eng_buf_load_set_dma_idx =
1932 pg_cmd_eng_buf_load_set_dma_idx_v0;
1933 g->ops.pmu_ver.get_perfmon_cntr_ptr = get_perfmon_cntr_ptr_v2;
1934 g->ops.pmu_ver.set_perfmon_cntr_ut = set_perfmon_cntr_ut_v2;
1935 g->ops.pmu_ver.set_perfmon_cntr_lt = set_perfmon_cntr_lt_v2;
1936 g->ops.pmu_ver.set_perfmon_cntr_valid =
1937 set_perfmon_cntr_valid_v2;
1938 g->ops.pmu_ver.set_perfmon_cntr_index =
1939 set_perfmon_cntr_index_v2;
1940 g->ops.pmu_ver.set_perfmon_cntr_group_id =
1941 set_perfmon_cntr_group_id_v2;
1942 g->ops.pmu_ver.get_perfmon_cntr_sz = pmu_perfmon_cntr_sz_v2;
1943 g->pmu_ver_cmd_id_zbc_table_update = 16;
1944 __nvgpu_set_enabled(g, NVGPU_PMU_ZBC_SAVE, true);
1945 g->ops.pmu_ver.get_pmu_cmdline_args_size =
1946 pmu_cmdline_size_v2;
1947 g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq =
1948 set_pmu_cmdline_args_cpufreq_v2;
1949 g->ops.pmu_ver.set_pmu_cmdline_args_secure_mode =
1950 set_pmu_cmdline_args_secure_mode_v2;
1951 g->ops.pmu_ver.set_pmu_cmdline_args_trace_size =
1952 set_pmu_cmdline_args_falctracesize_v2;
1953 g->ops.pmu_ver.set_pmu_cmdline_args_trace_dma_base =
1954 set_pmu_cmdline_args_falctracedmabase_v2;
1955 g->ops.pmu_ver.set_pmu_cmdline_args_trace_dma_idx =
1956 set_pmu_cmdline_args_falctracedmaidx_v2;
1957 g->ops.pmu_ver.get_pmu_cmdline_args_ptr =
1958 get_pmu_cmdline_args_ptr_v2;
1959 g->ops.pmu_ver.get_pmu_allocation_struct_size =
1960 get_pmu_allocation_size_v1;
1961 g->ops.pmu_ver.set_pmu_allocation_ptr =
1962 set_pmu_allocation_ptr_v1;
1963 g->ops.pmu_ver.pmu_allocation_set_dmem_size =
1964 pmu_allocation_set_dmem_size_v1;
1965 g->ops.pmu_ver.pmu_allocation_get_dmem_size =
1966 pmu_allocation_get_dmem_size_v1;
1967 g->ops.pmu_ver.pmu_allocation_get_dmem_offset =
1968 pmu_allocation_get_dmem_offset_v1;
1969 g->ops.pmu_ver.pmu_allocation_get_dmem_offset_addr =
1970 pmu_allocation_get_dmem_offset_addr_v1;
1971 g->ops.pmu_ver.pmu_allocation_set_dmem_offset =
1972 pmu_allocation_set_dmem_offset_v1;
1973 g->ops.pmu_ver.get_pmu_init_msg_pmu_queue_params =
1974 get_pmu_init_msg_pmu_queue_params_v1;
1975 g->ops.pmu_ver.get_pmu_msg_pmu_init_msg_ptr =
1976 get_pmu_msg_pmu_init_msg_ptr_v1;
1977 g->ops.pmu_ver.get_pmu_init_msg_pmu_sw_mg_off =
1978 get_pmu_init_msg_pmu_sw_mg_off_v1;
1979 g->ops.pmu_ver.get_pmu_init_msg_pmu_sw_mg_size =
1980 get_pmu_init_msg_pmu_sw_mg_size_v1;
1981 g->ops.pmu_ver.get_pmu_perfmon_cmd_start_size =
1982 get_pmu_perfmon_cmd_start_size_v1;
1983 g->ops.pmu_ver.get_perfmon_cmd_start_offsetofvar =
1984 get_perfmon_cmd_start_offsetofvar_v1;
1985 g->ops.pmu_ver.perfmon_start_set_cmd_type =
1986 perfmon_start_set_cmd_type_v1;
1987 g->ops.pmu_ver.perfmon_start_set_group_id =
1988 perfmon_start_set_group_id_v1;
1989 g->ops.pmu_ver.perfmon_start_set_state_id =
1990 perfmon_start_set_state_id_v1;
1991 g->ops.pmu_ver.perfmon_start_set_flags =
1992 perfmon_start_set_flags_v1;
1993 g->ops.pmu_ver.perfmon_start_get_flags =
1994 perfmon_start_get_flags_v1;
1995 g->ops.pmu_ver.get_pmu_perfmon_cmd_init_size =
1996 get_pmu_perfmon_cmd_init_size_v1;
1997 g->ops.pmu_ver.get_perfmon_cmd_init_offsetofvar =
1998 get_perfmon_cmd_init_offsetofvar_v1;
1999 g->ops.pmu_ver.perfmon_cmd_init_set_sample_buffer =
2000 perfmon_cmd_init_set_sample_buffer_v1;
2001 g->ops.pmu_ver.perfmon_cmd_init_set_dec_cnt =
2002 perfmon_cmd_init_set_dec_cnt_v1;
2003 g->ops.pmu_ver.perfmon_cmd_init_set_base_cnt_id =
2004 perfmon_cmd_init_set_base_cnt_id_v1;
2005 g->ops.pmu_ver.perfmon_cmd_init_set_samp_period_us =
2006 perfmon_cmd_init_set_samp_period_us_v1;
2007 g->ops.pmu_ver.perfmon_cmd_init_set_num_cnt =
2008 perfmon_cmd_init_set_num_cnt_v1;
2009 g->ops.pmu_ver.perfmon_cmd_init_set_mov_avg =
2010 perfmon_cmd_init_set_mov_avg_v1;
2011 g->ops.pmu_ver.get_pmu_seq_in_a_ptr =
2012 get_pmu_sequence_in_alloc_ptr_v1;
2013 g->ops.pmu_ver.get_pmu_seq_out_a_ptr =
2014 get_pmu_sequence_out_alloc_ptr_v1;
2015 break;
2016 case APP_VERSION_GM20B_1:
2017 case APP_VERSION_GM20B:
2018 case APP_VERSION_1:
2019 case APP_VERSION_2:
2020 case APP_VERSION_3:
2021 g->ops.pmu_ver.pg_cmd_eng_buf_load_size =
2022 pg_cmd_eng_buf_load_size_v0;
2023 g->ops.pmu_ver.pg_cmd_eng_buf_load_set_cmd_type =
2024 pg_cmd_eng_buf_load_set_cmd_type_v0;
2025 g->ops.pmu_ver.pg_cmd_eng_buf_load_set_engine_id =
2026 pg_cmd_eng_buf_load_set_engine_id_v0;
2027 g->ops.pmu_ver.pg_cmd_eng_buf_load_set_buf_idx =
2028 pg_cmd_eng_buf_load_set_buf_idx_v0;
2029 g->ops.pmu_ver.pg_cmd_eng_buf_load_set_pad =
2030 pg_cmd_eng_buf_load_set_pad_v0;
2031 g->ops.pmu_ver.pg_cmd_eng_buf_load_set_buf_size =
2032 pg_cmd_eng_buf_load_set_buf_size_v0;
2033 g->ops.pmu_ver.pg_cmd_eng_buf_load_set_dma_base =
2034 pg_cmd_eng_buf_load_set_dma_base_v0;
2035 g->ops.pmu_ver.pg_cmd_eng_buf_load_set_dma_offset =
2036 pg_cmd_eng_buf_load_set_dma_offset_v0;
2037 g->ops.pmu_ver.pg_cmd_eng_buf_load_set_dma_idx =
2038 pg_cmd_eng_buf_load_set_dma_idx_v0;
2039 g->pmu_ver_cmd_id_zbc_table_update = 16;
2040 __nvgpu_set_enabled(g, NVGPU_PMU_ZBC_SAVE, true);
2041 g->ops.pmu_ver.get_perfmon_cntr_ptr = get_perfmon_cntr_ptr_v0;
2042 g->ops.pmu_ver.set_perfmon_cntr_ut = set_perfmon_cntr_ut_v0;
2043 g->ops.pmu_ver.set_perfmon_cntr_lt = set_perfmon_cntr_lt_v0;
2044 g->ops.pmu_ver.set_perfmon_cntr_valid =
2045 set_perfmon_cntr_valid_v0;
2046 g->ops.pmu_ver.set_perfmon_cntr_index =
2047 set_perfmon_cntr_index_v0;
2048 g->ops.pmu_ver.set_perfmon_cntr_group_id =
2049 set_perfmon_cntr_group_id_v0;
2050 g->ops.pmu_ver.get_perfmon_cntr_sz = pmu_perfmon_cntr_sz_v0;
2051 g->ops.pmu_ver.get_pmu_cmdline_args_size =
2052 pmu_cmdline_size_v1;
2053 g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq =
2054 set_pmu_cmdline_args_cpufreq_v1;
2055 g->ops.pmu_ver.set_pmu_cmdline_args_secure_mode =
2056 set_pmu_cmdline_args_secure_mode_v1;
2057 g->ops.pmu_ver.set_pmu_cmdline_args_trace_size =
2058 set_pmu_cmdline_args_falctracesize_v1;
2059 g->ops.pmu_ver.set_pmu_cmdline_args_trace_dma_base =
2060 set_pmu_cmdline_args_falctracedmabase_v1;
2061 g->ops.pmu_ver.set_pmu_cmdline_args_trace_dma_idx =
2062 set_pmu_cmdline_args_falctracedmaidx_v1;
2063 g->ops.pmu_ver.get_pmu_cmdline_args_ptr =
2064 get_pmu_cmdline_args_ptr_v1;
2065 g->ops.pmu_ver.get_pmu_allocation_struct_size =
2066 get_pmu_allocation_size_v1;
2067 g->ops.pmu_ver.set_pmu_allocation_ptr =
2068 set_pmu_allocation_ptr_v1;
2069 g->ops.pmu_ver.pmu_allocation_set_dmem_size =
2070 pmu_allocation_set_dmem_size_v1;
2071 g->ops.pmu_ver.pmu_allocation_get_dmem_size =
2072 pmu_allocation_get_dmem_size_v1;
2073 g->ops.pmu_ver.pmu_allocation_get_dmem_offset =
2074 pmu_allocation_get_dmem_offset_v1;
2075 g->ops.pmu_ver.pmu_allocation_get_dmem_offset_addr =
2076 pmu_allocation_get_dmem_offset_addr_v1;
2077 g->ops.pmu_ver.pmu_allocation_set_dmem_offset =
2078 pmu_allocation_set_dmem_offset_v1;
2079 g->ops.pmu_ver.get_pmu_init_msg_pmu_queue_params =
2080 get_pmu_init_msg_pmu_queue_params_v1;
2081 g->ops.pmu_ver.get_pmu_msg_pmu_init_msg_ptr =
2082 get_pmu_msg_pmu_init_msg_ptr_v1;
2083 g->ops.pmu_ver.get_pmu_init_msg_pmu_sw_mg_off =
2084 get_pmu_init_msg_pmu_sw_mg_off_v1;
2085 g->ops.pmu_ver.get_pmu_init_msg_pmu_sw_mg_size =
2086 get_pmu_init_msg_pmu_sw_mg_size_v1;
2087 g->ops.pmu_ver.get_pmu_perfmon_cmd_start_size =
2088 get_pmu_perfmon_cmd_start_size_v1;
2089 g->ops.pmu_ver.get_perfmon_cmd_start_offsetofvar =
2090 get_perfmon_cmd_start_offsetofvar_v1;
2091 g->ops.pmu_ver.perfmon_start_set_cmd_type =
2092 perfmon_start_set_cmd_type_v1;
2093 g->ops.pmu_ver.perfmon_start_set_group_id =
2094 perfmon_start_set_group_id_v1;
2095 g->ops.pmu_ver.perfmon_start_set_state_id =
2096 perfmon_start_set_state_id_v1;
2097 g->ops.pmu_ver.perfmon_start_set_flags =
2098 perfmon_start_set_flags_v1;
2099 g->ops.pmu_ver.perfmon_start_get_flags =
2100 perfmon_start_get_flags_v1;
2101 g->ops.pmu_ver.get_pmu_perfmon_cmd_init_size =
2102 get_pmu_perfmon_cmd_init_size_v1;
2103 g->ops.pmu_ver.get_perfmon_cmd_init_offsetofvar =
2104 get_perfmon_cmd_init_offsetofvar_v1;
2105 g->ops.pmu_ver.perfmon_cmd_init_set_sample_buffer =
2106 perfmon_cmd_init_set_sample_buffer_v1;
2107 g->ops.pmu_ver.perfmon_cmd_init_set_dec_cnt =
2108 perfmon_cmd_init_set_dec_cnt_v1;
2109 g->ops.pmu_ver.perfmon_cmd_init_set_base_cnt_id =
2110 perfmon_cmd_init_set_base_cnt_id_v1;
2111 g->ops.pmu_ver.perfmon_cmd_init_set_samp_period_us =
2112 perfmon_cmd_init_set_samp_period_us_v1;
2113 g->ops.pmu_ver.perfmon_cmd_init_set_num_cnt =
2114 perfmon_cmd_init_set_num_cnt_v1;
2115 g->ops.pmu_ver.perfmon_cmd_init_set_mov_avg =
2116 perfmon_cmd_init_set_mov_avg_v1;
2117 g->ops.pmu_ver.get_pmu_seq_in_a_ptr =
2118 get_pmu_sequence_in_alloc_ptr_v1;
2119 g->ops.pmu_ver.get_pmu_seq_out_a_ptr =
2120 get_pmu_sequence_out_alloc_ptr_v1;
2121 break;
2122 case APP_VERSION_0:
2123 g->ops.pmu_ver.pg_cmd_eng_buf_load_size =
2124 pg_cmd_eng_buf_load_size_v0;
2125 g->ops.pmu_ver.pg_cmd_eng_buf_load_set_cmd_type =
2126 pg_cmd_eng_buf_load_set_cmd_type_v0;
2127 g->ops.pmu_ver.pg_cmd_eng_buf_load_set_engine_id =
2128 pg_cmd_eng_buf_load_set_engine_id_v0;
2129 g->ops.pmu_ver.pg_cmd_eng_buf_load_set_buf_idx =
2130 pg_cmd_eng_buf_load_set_buf_idx_v0;
2131 g->ops.pmu_ver.pg_cmd_eng_buf_load_set_pad =
2132 pg_cmd_eng_buf_load_set_pad_v0;
2133 g->ops.pmu_ver.pg_cmd_eng_buf_load_set_buf_size =
2134 pg_cmd_eng_buf_load_set_buf_size_v0;
2135 g->ops.pmu_ver.pg_cmd_eng_buf_load_set_dma_base =
2136 pg_cmd_eng_buf_load_set_dma_base_v0;
2137 g->ops.pmu_ver.pg_cmd_eng_buf_load_set_dma_offset =
2138 pg_cmd_eng_buf_load_set_dma_offset_v0;
2139 g->ops.pmu_ver.pg_cmd_eng_buf_load_set_dma_idx =
2140 pg_cmd_eng_buf_load_set_dma_idx_v0;
2141 g->pmu_ver_cmd_id_zbc_table_update = 14;
2142 __nvgpu_set_enabled(g, NVGPU_PMU_ZBC_SAVE, true);
2143 g->ops.pmu_ver.get_perfmon_cntr_ptr = get_perfmon_cntr_ptr_v0;
2144 g->ops.pmu_ver.set_perfmon_cntr_ut = set_perfmon_cntr_ut_v0;
2145 g->ops.pmu_ver.set_perfmon_cntr_lt = set_perfmon_cntr_lt_v0;
2146 g->ops.pmu_ver.set_perfmon_cntr_valid =
2147 set_perfmon_cntr_valid_v0;
2148 g->ops.pmu_ver.set_perfmon_cntr_index =
2149 set_perfmon_cntr_index_v0;
2150 g->ops.pmu_ver.set_perfmon_cntr_group_id =
2151 set_perfmon_cntr_group_id_v0;
2152 g->ops.pmu_ver.get_perfmon_cntr_sz = pmu_perfmon_cntr_sz_v0;
2153 g->ops.pmu_ver.get_pmu_cmdline_args_size =
2154 pmu_cmdline_size_v0;
2155 g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq =
2156 set_pmu_cmdline_args_cpufreq_v0;
2157 g->ops.pmu_ver.set_pmu_cmdline_args_secure_mode =
2158 NULL;
2159 g->ops.pmu_ver.get_pmu_cmdline_args_ptr =
2160 get_pmu_cmdline_args_ptr_v0;
2161 g->ops.pmu_ver.get_pmu_allocation_struct_size =
2162 get_pmu_allocation_size_v0;
2163 g->ops.pmu_ver.set_pmu_allocation_ptr =
2164 set_pmu_allocation_ptr_v0;
2165 g->ops.pmu_ver.pmu_allocation_set_dmem_size =
2166 pmu_allocation_set_dmem_size_v0;
2167 g->ops.pmu_ver.pmu_allocation_get_dmem_size =
2168 pmu_allocation_get_dmem_size_v0;
2169 g->ops.pmu_ver.pmu_allocation_get_dmem_offset =
2170 pmu_allocation_get_dmem_offset_v0;
2171 g->ops.pmu_ver.pmu_allocation_get_dmem_offset_addr =
2172 pmu_allocation_get_dmem_offset_addr_v0;
2173 g->ops.pmu_ver.pmu_allocation_set_dmem_offset =
2174 pmu_allocation_set_dmem_offset_v0;
2175 g->ops.pmu_ver.get_pmu_init_msg_pmu_queue_params =
2176 get_pmu_init_msg_pmu_queue_params_v0;
2177 g->ops.pmu_ver.get_pmu_msg_pmu_init_msg_ptr =
2178 get_pmu_msg_pmu_init_msg_ptr_v0;
2179 g->ops.pmu_ver.get_pmu_init_msg_pmu_sw_mg_off =
2180 get_pmu_init_msg_pmu_sw_mg_off_v0;
2181 g->ops.pmu_ver.get_pmu_init_msg_pmu_sw_mg_size =
2182 get_pmu_init_msg_pmu_sw_mg_size_v0;
2183 g->ops.pmu_ver.get_pmu_perfmon_cmd_start_size =
2184 get_pmu_perfmon_cmd_start_size_v0;
2185 g->ops.pmu_ver.get_perfmon_cmd_start_offsetofvar =
2186 get_perfmon_cmd_start_offsetofvar_v0;
2187 g->ops.pmu_ver.perfmon_start_set_cmd_type =
2188 perfmon_start_set_cmd_type_v0;
2189 g->ops.pmu_ver.perfmon_start_set_group_id =
2190 perfmon_start_set_group_id_v0;
2191 g->ops.pmu_ver.perfmon_start_set_state_id =
2192 perfmon_start_set_state_id_v0;
2193 g->ops.pmu_ver.perfmon_start_set_flags =
2194 perfmon_start_set_flags_v0;
2195 g->ops.pmu_ver.perfmon_start_get_flags =
2196 perfmon_start_get_flags_v0;
2197 g->ops.pmu_ver.get_pmu_perfmon_cmd_init_size =
2198 get_pmu_perfmon_cmd_init_size_v0;
2199 g->ops.pmu_ver.get_perfmon_cmd_init_offsetofvar =
2200 get_perfmon_cmd_init_offsetofvar_v0;
2201 g->ops.pmu_ver.perfmon_cmd_init_set_sample_buffer =
2202 perfmon_cmd_init_set_sample_buffer_v0;
2203 g->ops.pmu_ver.perfmon_cmd_init_set_dec_cnt =
2204 perfmon_cmd_init_set_dec_cnt_v0;
2205 g->ops.pmu_ver.perfmon_cmd_init_set_base_cnt_id =
2206 perfmon_cmd_init_set_base_cnt_id_v0;
2207 g->ops.pmu_ver.perfmon_cmd_init_set_samp_period_us =
2208 perfmon_cmd_init_set_samp_period_us_v0;
2209 g->ops.pmu_ver.perfmon_cmd_init_set_num_cnt =
2210 perfmon_cmd_init_set_num_cnt_v0;
2211 g->ops.pmu_ver.perfmon_cmd_init_set_mov_avg =
2212 perfmon_cmd_init_set_mov_avg_v0;
2213 g->ops.pmu_ver.get_pmu_seq_in_a_ptr =
2214 get_pmu_sequence_in_alloc_ptr_v0;
2215 g->ops.pmu_ver.get_pmu_seq_out_a_ptr =
2216 get_pmu_sequence_out_alloc_ptr_v0;
2217 break;
2218 default: 1507 default:
2219 nvgpu_err(g, "PMU code version not supported version: %d\n", 1508 nvgpu_err(g, "PMU code version not supported version: %d\n",
2220 pmu->desc->app_version); 1509 pmu->desc->app_version);
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-04 22:31:40 -0400