gpu: nvgpu: common: fix MISRA 10.4 violations

MISRA Rule 10.4 only allows the usage of arithmetic operations on
operands of the same essential type category.

Adding "U" at the end of the integer literals to have same type of
operands when an arithmetic operation is performed.

This fix violations where an arithmetic operation is performed on
signed and unsigned int types.

Jira NVGPU-992

Change-Id: Iab512139a025e035ec82a9dd74245bcf1f3869fb
Signed-off-by: Sai Nikhil <snikhil@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1789425
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 3 insertions, 3 deletions

diff --git a/drivers/gpu/nvgpu/common/pmu/pmu.c b/drivers/gpu/nvgpu/common/pmu/pmu.c
index d72629b5..86e56d9e 100644
--- a/drivers/gpu/nvgpu/common/pmu/pmu.c
+++ b/drivers/gpu/nvgpu/common/pmu/pmu.c
@@ -512,7 +512,7 @@ int nvgpu_pmu_destroy(struct gk20a *g)
 {
         struct nvgpu_pmu *pmu = &g->pmu;
         struct pmu_pg_stats_data pg_stat_data = { 0 };
-        int i;
+        u32 i;
 
         nvgpu_log_fn(g, " ");
 
@@ -539,7 +539,7 @@ int nvgpu_pmu_destroy(struct gk20a *g)
         pmu->isr_enabled = false;
         nvgpu_mutex_release(&pmu->isr_mutex);
 
-        for (i = 0; i < PMU_QUEUE_COUNT; i++) {
+        for (i = 0U; i < PMU_QUEUE_COUNT; i++) {
                 nvgpu_flcn_queue_free(pmu->flcn, &pmu->queue[i]);
         }
 
@@ -559,7 +559,7 @@ void nvgpu_pmu_surface_describe(struct gk20a *g, struct nvgpu_mem *mem,
 {
         fb->address.lo = u64_lo32(mem->gpu_va);
         fb->address.hi = u64_hi32(mem->gpu_va);
-        fb->params = ((u32)mem->size & 0xFFFFFF);
+        fb->params = ((u32)mem->size & 0xFFFFFFU);
         fb->params |= (GK20A_PMU_DMAIDX_VIRT << 24);
 }