diff options
author | Debarshi Dutta <ddutta@nvidia.com> | 2018-08-22 00:27:01 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-08-29 20:46:51 -0400 |
commit | 74639b444251d7adc222400625eb59a3d53d0c0a (patch) | |
tree | 19373fbe8ee522863c990fdfa0db24e6474f5167 /drivers/gpu/nvgpu/common/pmu/pmu.c | |
parent | e3710e5431d8f14f1b8c2812f5c1aeeb7bdaac1c (diff) |
gpu: nvgpu: invoke calls to methods in pmu_gk20a.h via HAL
In nvgpu repository, we have multiple accesses to methods in
pmu_gk20a.h which have register accesses. Instead of directly invoking
these methods, these are now called via HALs. Some common methods such
as pmu_wait_message_cond which donot have any register accesses
are moved to pmu_ipc.c and the method declarations are moved
to pmu.h. Also, changed gm20b_pmu_dbg to
nvgpu_dbg_pmu all across the code base. This would remove all
indirect dependencies via gk20a.h into pmu_gk20a.h. As a result
pmu_gk20a.h is now removed from gk20a.h
JIRA-597
Change-Id: Id54b2684ca39362fda7626238c3116cd49e92080
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1804283
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/common/pmu/pmu.c')
-rw-r--r-- | drivers/gpu/nvgpu/common/pmu/pmu.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/common/pmu/pmu.c b/drivers/gpu/nvgpu/common/pmu/pmu.c index 86e56d9e..0395e463 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu.c +++ b/drivers/gpu/nvgpu/common/pmu/pmu.c | |||
@@ -81,7 +81,7 @@ static int pmu_enable(struct nvgpu_pmu *pmu, bool enable) | |||
81 | 81 | ||
82 | if (!enable) { | 82 | if (!enable) { |
83 | if (!g->ops.pmu.is_engine_in_reset(g)) { | 83 | if (!g->ops.pmu.is_engine_in_reset(g)) { |
84 | pmu_enable_irq(pmu, false); | 84 | g->ops.pmu.pmu_enable_irq(pmu, false); |
85 | pmu_enable_hw(pmu, false); | 85 | pmu_enable_hw(pmu, false); |
86 | } | 86 | } |
87 | } else { | 87 | } else { |
@@ -95,7 +95,7 @@ static int pmu_enable(struct nvgpu_pmu *pmu, bool enable) | |||
95 | goto exit; | 95 | goto exit; |
96 | } | 96 | } |
97 | 97 | ||
98 | pmu_enable_irq(pmu, true); | 98 | g->ops.pmu.pmu_enable_irq(pmu, true); |
99 | } | 99 | } |
100 | 100 | ||
101 | exit: | 101 | exit: |
@@ -412,7 +412,7 @@ static void pmu_setup_hw_enable_elpg(struct gk20a *g) | |||
412 | if (nvgpu_is_enabled(g, NVGPU_PMU_ZBC_SAVE)) { | 412 | if (nvgpu_is_enabled(g, NVGPU_PMU_ZBC_SAVE)) { |
413 | /* Save zbc table after PMU is initialized. */ | 413 | /* Save zbc table after PMU is initialized. */ |
414 | pmu->zbc_ready = true; | 414 | pmu->zbc_ready = true; |
415 | gk20a_pmu_save_zbc(g, 0xf); | 415 | g->ops.gr.pmu_save_zbc(g, 0xf); |
416 | } | 416 | } |
417 | 417 | ||
418 | if (g->elpg_enabled) { | 418 | if (g->elpg_enabled) { |